Non-volatile memory device with non-evenly distributable data access

• US 8,539,195 B2
• Filed: 07/10/2012
• Issued: 09/17/2013
• Est. Priority Date: 02/09/2007
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell World Trade Limited (Marvell Technology Group Limited)
• Inventors: Wu, Zining, Nguyen, Lau, Sutardja, Pantas, Lee, Chi-Kong, Yoon, Tony
• Primary Examiner(s): Bertram, Ryan
• Application Number:
  US13/545,508
• Publication Number:
  US 20120278545A1
• Time in Patent Office: 434 Days
• Field of Search: 711/103, 711/154, 711/171
• US Class Current: 711/171
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

A system includes chips and a control module. Each of the chips includes an array of memory cells. Each of the arrays of memory cells includes rows of memory cells. Each of the rows of memory cells is configured to store a predetermined amount of data. The control module is configured to receive data, encode the data to generate blocks of encoded data, store a first portion of one of the blocks of encoded data in a first selected number row of a first chip, and store a remaining portion of the one of the blocks of encoded data in a second selected number row of a second chip. An amount of data in each of the blocks of encoded data is more than the predetermined amount of data. The second selected number row is a same number row or a higher number row than the first selected number row.

Claims

1. A system comprising:

a plurality of chips comprising a first chip and a second chip, wherein each of the plurality of chips comprise an array of memory cells, wherein each of the arrays of memory cells comprises rows of memory cells, and wherein each of the rows of memory cells is configured to store a predetermined amount of data; and

a control module configured to (i) receive data, (ii) encode the data to generate blocks of encoded data, (iii) store a first portion of one of the blocks of encoded data in a first selected number row of the first chip, and (iv) store a remaining portion of the one of the blocks of encoded data in a second selected number row of the second chip, wherein an amount of data in each of the blocks of encoded data is more than the predetermined amount of data, and wherein the second selected number row is a same number row or a higher number row than the first selected number row.

2. The system of claim 1, wherein the first selected number row is a same number row as the second selected number row.

3. The system of claim 1, wherein the second selected number row is a number row one higher than the first selected number row.

4. The system of claim 1, wherein:

the blocks of encoded data are arranged in a logical data structure format; and

the logical data structure format includes at least one of a logical page of data and a logical block of data; and

the control module is configured to store the blocks of encoded data based on the logical data structure format.

5. The system of claim 1, wherein:

the blocks of encoded data comprise a logical page of data;

the logical page of data comprises a first portion and a remaining portion; and

the control module is configured store (i) the first portion of the logical page of data in a first array of the first chip, and (ii) the remaining portion of the logical page of data in a second array of the second chip.

6. The system of claim 1, wherein:

the blocks of encoded data comprise a logical block of data;

the logical block of data comprises a first portion and a remaining portion; and

the control module is configured store (i) the first portion of the logical block of data in a first array of the first chip, and (ii) the remaining portion of the logical block of data in a second array of the second chip.

7. The system of claim 1, wherein:

the encoded blocks of data comprise a first encoded block of data and a second encoded block of data;

the first chip comprises a physical page of memory cells; and

the control module is configured to allocate (i) a first portion of the physical page of memory cells for storing a first portion of the first encoded block of data, and (ii) a remaining portion of the physical page of memory cells for storing a first portion of the second encoded block of data.

8. The system of claim 7, wherein the control module is configured to allocate (i) the first portion of the physical page of memory cells for storing a remaining portion of the first encoded block of data, and (ii) the remaining portion of the physical page of memory cells for storing the remaining portion of the second encoded block of data.

9. The system of claim 7, wherein:

the second chip comprises a second physical page of memory cells; and

the control module is configured to allocate (i) a first portion of the second physical page of memory cells for storing a remaining portion of the first encoded block of data, and (ii) a remaining portion of the second physical page of memory cells for storing the remaining portion of the second encoded block of data.

10. The system of claim 1, wherein the control module is configured to (i) select one of a plurality of error correction code rates prior to encoding the data to generate blocks of encoded data, and (ii) generate the blocks of encoded data based on the selected error correction code rate.

11. The system of claim 1, wherein the control module is configured to store the first portion of the one of the blocks of encoded data in the first selected number row of the first chip while storing the remaining portion of the one of the blocks of encoded data in the second selected number row of the second chip.

12. The system of claim 1, wherein:

the blocks of encoded data comprise a first encoded block of data and a second encoded block of data;

the first chip comprises a first array of memory cells;

the second chip comprises a second array of memory cells; and

the control module is configured to store a first portion of the first encoded block of data in the first array of memory cells while storing a second portion of the first encoded block of data in the second array of memory cells.

13. The system of claim 12, wherein the control module is configured to store a first portion of the second encoded block of data in the second array of memory cells while storing (i) the first portion of the first encoded block of data in the first array of memory cells, and (ii) the second portion of the first encoded block of data in the second array of memory cells.

14. A method comprising:

receiving data;

encoding the data to generate blocks of encoded data;

storing a first portion of one of the blocks of encoded data in a first selected number row of a first chip of a plurality of chips; and

storing a remaining portion of the one of the blocks of encoded data in a second selected number row of a second chip of the plurality of chips, wherein the second selected number row is a same number row or a higher number row than the first selected number row, and wherein

each of the plurality of chips comprises an array of memory cells,

each of the arrays of memory cells comprises rows of memory cells,

each of the rows of memory cells is configured to store a predetermined amount of data, and

an amount of data in each of the blocks of encoded data is more than the predetermined amount of data.

15. The method of claim 14, further comprising storing (i) a first portion of a logical page of data in a first array of the first chip, and (ii) a remaining portion of the logical page of data in a second array of the second chip,

wherein the blocks of encoded data comprise the logical page of data.

16. The method of claim 14, further comprising storing (i) a first portion of a logical block of data in a first array of the first chip, and (ii) a remaining portion of the logical block of data in a second array of the second chip,

wherein the blocks of encoded data comprise the logical block of data.

17. The method of claim 14, further comprising allocating (i) a first portion of a physical page of memory cells for storing a first portion of a first encoded block of data, and (ii) a remaining portion of the physical page of memory cells for storing a first portion of a second encoded block of data,

wherein the first chip comprises the physical page of memory cells.

18. The method of claim 17, further comprising allocating (i) the first portion of the physical page of memory cells for storing a remaining portion of the first encoded block of data, and (ii) the remaining portion of the physical page of memory cells for storing the remaining portion of the second encoded block of data.

19. The method of claim 17, further comprising allocating (i) a first portion of a second physical page of memory cells for storing a remaining portion of the first encoded block of data, and (ii) a remaining portion of the second physical page of memory cells for storing the remaining portion of the second encoded block of data,

wherein the second chip comprises the second physical page of memory cells.

20. The method of claim 14, further comprising:

storing a first portion of a first encoded block of data in a first array of memory cells while storing a second portion of the first encoded block of data in a second array of memory cells, wherein the first chip comprises the first array of memory cells, and wherein the second chip comprises the second array of memory cells; and

storing a first portion of a second encoded block of data in the second array of memory cells while storing (i) the first portion of the first encoded block of data in the first array of memory cells, and (ii) the second portion of the first encoded block of data in the second array of memory cells.