Context switching with automatic saving of special function registers memory-mapped to all banks

• US 8,539,210 B2
• Filed: 06/27/2008
• Issued: 09/17/2013
• Est. Priority Date: 11/30/2007
• Status: Active Grant

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Julicher, Joseph, Smit, Zacharias Marthinus, Steedman, Sean, Delport, Vivien, Zdenek, Jerrold S., Ellison, Ryan Scott, Schroeder, Eric
• Primary Examiner(s): VICARY, KEITH E
• Application Number:
  US12/147,746
• Publication Number:
  US 20090144481A1
• Time in Patent Office: 1,908 Days
• Field of Search: 712/228
• US Class Current: 712/228
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context

Abstract

A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Claims

1. A microprocessor or microcontroller device comprising:

a central processing unit (CPU);

a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks; and

a plurality of special function registers that are memory-mapped to the data memory, wherein a first set of special function registers from said plurality of memory-mapped special function registers is memory-mapped to all memory banks; and

wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the first set of special function registers into a second set of special function registers from said plurality of memory-mapped special function registers and upon return from said context switch restore the content of the first set of special function registers from the second set of special function registers.

2. The device according to claim 1, further comprising an interrupt unit coupled with the CPU, wherein said context switch is induced by an interrupt.

3. The device according to claim 1, wherein said context switch is software induced.

4. The device according to claim 1, wherein the first set of special function registers comprises:

a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch.

5. The device according to claim 1, wherein the first set of special function registers comprises:

a plurality of indirect addressing mode registers which cause an indirect addressing access upon a read or write access to one of said indirect addressing mode registers;

a first program counter register;

a status register,

a plurality of indirect memory address registers;

a bank select register,

a working register,

a program counter high latch register, and

an interrupt control register.

6. The device according to claim 5, wherein said first set of special function registers is mapped starting at memory bank address 0.

7. The device according to claim 6, comprising two indirect addressing mode registers and four indirect memory address registers, wherein access to an indirect addressing mode register uses two concatenated indirect memory address registers of said four indirect memory address registers and wherein said first set of special function registers is mapped from memory bank address 0 to 0Bh.

8. The device according to claim 1, further comprising a program memory coupled with said CPU, wherein a bit in an indirect memory address register indicates whether an indirect memory access is performed on said data memory or said program memory.

9. A method of operating a microprocessor or microcontroller device comprising a central processing unit (CPU);

a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks;

a plurality of special function registers that are memory-mapped to the data memory, the method comprising the steps of;

memory-mapping a first set of special function registers from said plurality of memory-mapped special function registers to all memory banks;

upon occurrence of a context switch, saving automatically the content of the first set of special function registers into a second set of special function registers from said plurality of memory-mapped special function registers, and upon return from said context switch restoring the content of the first set of special function registers from the second set of special function registers.

10. The method according to claim 9, further comprising inducing said context switch by an interrupt.

11. The method according to claim 9, wherein said context switch is software induced.

12. The method according to claim 9, wherein the first set of special function registers comprises:

a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch.

13. The method according to claim 9, wherein the first set of special function registers comprises:

a plurality of indirect addressing mode registers which cause an indirect addressing access upon a read or write access to one of said indirect addressing mode registers;

a first program counter register;

a status register,

a plurality of indirect memory address registers;

a bank select register,

a working register,

a program counter high latch register, and

an interrupt control register.

14. The method according to claim 13, wherein said first set of special function registers is mapped starting at memory bank address 0.

15. The method according to claim 13, using two indirect addressing mode registers and four indirect memory address registers, wherein access to an indirect addressing mode register uses two concatenated indirect memory address registers of said four indirect memory address registers and wherein said first set of special function registers is mapped from memory bank address 0 to 0Bh.

16. The method according to claim 9, using a program memory coupled with said CPU, wherein a bit in an indirect memory address register indicates whether an indirect memory access is performed on said data memory or said program memory.