Low overhead error correcting code protection for stored information

• US 8,539,303 B2
• Filed: 12/20/2010
• Issued: 09/17/2013
• Est. Priority Date: 12/20/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lu, Shih-Lien L., Somasekhar, Dinesh
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US12/973,880
• Publication Number:
  US 20120159283A1
• Time in Patent Office: 1,002 Days
• Field of Search: 714/755, 714/758, 714/766, 714/807
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values.

Claims

1. An apparatus comprising:

a data storage structure to store a plurality of first data values, each of the plurality of first data values having a first data width;

a first check value storage structure to store a plurality of first check values;

a second check value storage structure to store a plurality of second check values; and

check value generation hardware to generate the first check values and the second check values, the first check values providing a first level of error protection for the first data values, the second check values providing a second level of error protection for a plurality of second data values, each of the plurality of second data values having a second data width, the second data width being greater than the first data width, each of the second data values being a concatenation of one of the first data values and at least another of the first data values;

wherein the memory array is to store each of the first data values in a one of a plurality of first locations; and

the check value generation hardware is also to generate a plurality of third check values from the contents of the plurality of first locations, compare each of the plurality of third check values to each of the plurality of first check values, generate a plurality of fourth check values from contents of the data storage structure where the plurality of second data values are stored, only if a third check value and a corresponding first check value do not match, compare each of the plurality of fourth check values to a corresponding second check value, wherein comparing a fourth check value to a second check value includes generating a syndrome; and

use the syndrome to correct the contents of the corresponding first location, wherein using the syndrome includes using only the columns in a parity check matrix that correspond to the first location of a byte of the data storage structure.

2. The apparatus of claim 1, wherein the data storage structure is a memory array arranged in a plurality of banks, and each of the second data values is a concatenation of one of the first data values from each bank.

3. The apparatus of claim 2, wherein each of the one of the first data values from each bank is at the same location within each bank.

4. The apparatus of claim 2, wherein the memory array is a cache memory.

5. The apparatus of claim 1, wherein the first data width is a byte.

6. The apparatus of claim 1, wherein the second data width is sixty-four bits.

7. The apparatus of claim 1, wherein the first level of error protection is parity.

8. The apparatus of claim 1, wherein the second level of error protection is single error correction, double error detection.

9. The apparatus of claim 1, wherein the plurality of first check values is a plurality of parity values.

10. The apparatus of claim 1, wherein the plurality of second check values is a plurality of error correction code values.

11. The apparatus of claim 1, wherein each of the plurality of second check values is generated and stored without a read-modify-write operation.

12. A method comprising:

generating a first check value to provide a first level of error protection for a first data value, the first data value having a first data width;

generating a second check value to provide a second level of error protection for a second data value, the second data value having a second data width, the second data width being greater than the first data width, the second data values being a concatenation of the first data values and at least a third data value, the third data value having the first data width; and

storing the first data value in a first location in a memory array;

storing the first check value in the memory array;

storing the second check value in the memory array;

reading the contents of the first location from the memory array;

generating a third check value from the contents read from the first location;

comparing the third check value to the first check value;

generating a fourth check value from contents of the memory array where the second data value is stored, only if the third check value and the first check value do not match

comparing the fourth check value to the second check value, wherein comparing the fourth check value to the second check value includes generating a syndrome; and

using the syndrome to correct the contents of the first location of the memory array, wherein using the syndrome to correct the contents of the first location of the memory array includes using only the columns in a parity check matrix that correspond to the first location of a byte of the memory array.

13. The method of claim 12, wherein the third data value is stored at the first location in a separate bank of the memory array.

14. The method of claim 12, wherein the memory array is a cache.

15. The method of claim 12, wherein storing the second check value in the memory array is done without a read-modify-write operation.

16. A system comprising:

a system memory; and

a processor having;

a cache to store a plurality of first data values from the system memory, a plurality of first check values, and a plurality of second check values, each of the plurality of first data values having a first data width; and

check value generation hardware to generate the first check values and the second check values, the first check values providing a first level of error protection for the first data values, the second check values providing a second level of error protection for a plurality of second data values, each of the plurality of data values having a second data width, the second data width being greater than the first data width, each of the second data values being a concatenation of one of the first data values and at least another of the first data values;

wherein the cache is to store each of the first data values in a one of a plurality of first locations; and

the check value generation hardware is also to generate a plurality of third check values from the contents of the plurality of first locations, compare each of the plurality of third check values to each of the plurality of first check values, generate a plurality of fourth check values from contents of the cache where the plurality of second data values are stored, only if a third check value and a corresponding first check value do not match, compare each of the plurality of fourth check values to a corresponding second check value, wherein comparing a fourth check value to a second check value includes generating a syndrome; and

use the syndrome to correct the contents of the corresponding first location, wherein using the syndrome includes using only the columns in a parity check matrix that correspond to the first location of a byte of the cache.