Data processing apparatus and method, and program

• US 8,539,322 B2
• Filed: 10/27/2009
• Issued: 09/17/2013
• Est. Priority Date: 10/27/2008
• Status: Active Grant

• Current Assignee: Saturn Licensing LLC (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Miyauchi, Toshiyuki, Yoshimochi, Naoki
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US13/125,111
• Publication Number:
  US 20110246863A1
• Time in Patent Office: 1,421 Days
• Field of Search: None
• US Class Current: 714/788
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11B 20/1866 by interleaving G11B20/1809 takes precedence
• CPC Class Codes: G11B 20/1876 Interpolating methods
• CPC Class Codes: G11B 2020/1853 using a product code which has inner and outer parity symbols
• CPC Class Codes: G11B 2220/2516 Hard disks
• CPC Class Codes: G11B 2220/2537 Optical discs
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/15 Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes H03M13/17 takes precedence
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/2707 Simple row-column interleaver, i.e. pure block interleaving
• CPC Class Codes: H03M 13/2721 the interleaver involves a diagonal direction, e.g. by using an interleaving matrix with read-out in a diagonal direction
• CPC Class Codes: H03M 13/2778 Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
• CPC Class Codes: H03M 13/2909 Product codes
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding

Abstract

The present invention relates to data processing apparatus and method, and a program which make it possible to scatter burst errors with respect to both codes of a product code.

A block-wise interleaver performs interleaving A, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the direction diagonally downward to the right, NB bits by NB bits (=block by block) with respect to ND×NB×NA bits of a product code. Next, the block-wise interleaver performs interleaving B, which is a process of inputting data in the order of the column direction as one direction, and reading the data in the order of the row direction as the other direction, NB bits by NB bits with respect to (NC−ND)×NB×NA bits representing the parity portion of an inner code indicated by P, of the product code. The present invention can be applied to, for example, a recording/reproducing apparatus.

Claims

1. A data processing apparatus having a processor, comprising:

an interleaver for performing interleaving on a product code to change a recording order, the product code being encoded in the order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with n bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits,

wherein in the recording order after the interleaving is performed by the interleaver, the same codeword of the inner code is not included in i consecutive bits, and j (j>

i) consecutive bits do not span a plurality of symbols of the same codeword of the outer code, i representing the number of pieces of the inner codes included in one product code and j representing a predetermined integral multiple of the of i and n.

2. The data processing apparatus according to claim 1, wherein the interleaver includes:

a first interleaver for performing first interleaving of NA×

NC blocks with NB (NB=n) bits as one block, by using NA pieces of the inner code; and

a second interleaver for performing second interleaving of NA×

NB bits NC times in units of bits, after the first interleaving by the first interleaver,

wherein NA represents the number of pieces of inner codes of one product code, NB represents the number of bits of one unit, and NC represents the number of units of one piece of the inner code.

3. The data processing apparatus according to claim 2, wherein the first interleaver performs the first interleaving by outputting the NA×

NC blocks, which are inputted in the order of one direction, in the order of a diagonal direction.

4. The data processing apparatus according to claim 2, wherein:

the first interleaving by the first interleaver includes;

interleaving in units of ND×

NB×

NA bits (ND×

NB≧

information length of the inner code), ND representing the number of units of user data in a row direction, and

interleaving of a portion of the product code that has not been interleaved by the first interleaver; and

the first interleaver performs the first interleaving by outputting NA×

ND blocks, which are inputted in the order of one direction, in the order of a diagonal direction, with respect to a range of the ND×

NB×

NA bits, and then outputting NA×

(NC−

ND) blocks, which are inputted in the order of the one direction, in the order of the other direction, with respect to a range of (NC−

ND)×

NB×

NA bits.

5. The data processing apparatus according to claim 4, wherein NA and ND are disjoint.

6. The data processing apparatus according to claim 5, wherein letting the index of blocks generated by dividing the inner code in units of NB bits be x=0, 1, . . . , ND−

1 in serial order, letting the index of the inner code be y=0, 1, NA−

1 in serial order, letting the x-th block of the y-th inner code be (x, y), and letting k be a variable that counts the number of blocks to be read, with respect to the range of the ND×

NB×

NA bits, the first interleaver outputs, from the inner code with the smallest index, the blocks inputted in ascending order of the index of the blocks, in the order of blocks (x, y) represented by

x=(k mod ND)

y=(k mod NA)

k=0, 1, 2, . . . , N−

1.

7. The data processing apparatus according to claim 2, wherein the second interleaver performs the second interleaving by:

performing processing in serial order NA blocks by NA blocks, with respect to the blocks on which the first interleaving has been performed by the first interleaver, and

outputting, within a range of the NA blocks, the first bit of each of the blocks in order, then outputting the second bit of each of the blocks in order, thereafter repeating the same processing and lastly, outputting the NB-th bit of each of the blocks in order.

8. The data processing apparatus according to claim 2, wherein a cycle, of the interleaving is smaller than one codeword of the product code.

9. A data processing method performed by a processor that performs interleaving on a product code encoded in the order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with a bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits. the ata processing method comprising the steps of:

performing the interleaving on the product code to change a recording order, so that in the recording order after the interleaving is performed, the same codeword of the inner code is not included in i consecutive bits, and j (j>

i) consecutive Bits do not span a plurality of symbols of the same codeword of the outer code, i representing, the number of pieces of the inner codes included in one product code j representing a predetermined integral multiple of the product of i and n.

10. A non-transitory storage medium storing an executable program for causing a data processing apparatus to execute a data processing method, the data processing apparatus performing interleaving on a product code encoded in the order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with n bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits, the data processing method comprising the steps of:

performing the interleaving on the product code to change a recording order, so that in the recording order after the interleaving is performed, the same codeword of the inner code is not included in i consecutive bits, and j(j>

i) consecutive bits do not span a plurality of symbols of the same codeword of the outer code, i representing the number of pieces of the inner codes included in one product code and j representing a predetermined integral multiple of the product of i and n.

11. A data processing apparatus, comprising:

a deinterleaver for performing deinterleaving on data read from a recording medium on which the data is recorded, to rearrange the data into an original order, the data being obtained by performing interleaving on a product code, which is encoded in the order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with n bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits, so that in a recording order after the interleaving is performed, the same codeword of the inner code is not included in i consecutive bits, and j (j>

i) consecutive bits do not span a plurality of symbols of the same codeword of the outer code, i representing the number of pieces of the inner code included in one product code and j representing a predetermined integral multiple of the product i an n.

12. The data processing apparatus according to claim 11, wherein the deinterleaver includes:

a first deinterleaver for performing first deinterleaving of NA×

NB bits NC times in units of bits; and

a second deinterleaver for performing second deinterleaving of NA×

NC blocks with NB (NB=n) bits as one block, by using NA pieces of the inner code, after the first deinterleaving by the first deinterleaver,

wherein NA represents the number of pieces of inner codes of one product code, NB represents the number of bits of one unit and NC represents the number of units one piece of the inner code.

13. The data processing apparatus according to claim 12, wherein the second deinterleaver outputs the NA×

NC blocks, which are inputted in the order of a diagonal direction, in the order of one direction.

14. The data processing apparatus according to claim 12, wherein:

the second deinterleaving by the second deinterleaver includes deinterleaving in units of ND×

NB×

NA bits (ND×

NB≧

information length of the inner code), and deinterleaving of a portion of the product code that has not been deinterleaved by the second deinterleaver, ND representing the number of units of user data in a row direction; and

the second deinterleaver outputs the NA×

NC blocks, which are inputted in the order of a diagonal direction, in the order of one direction, with respect to a range of the ND×

NB×

NA bits, and then outputs NA×

(NC−

ND) blocks, which are inputted in the order of the other direction, in the order of the one direction, with respect to a range of (NC−

ND)×

NB×

NA bits.

15. The data processing apparatus according to claim 14, wherein NA and ND are disjoint.

16. The data processing apparatus according to claim 15, wherein letting the index of blocks generated by dividing the inner code in units of NB bits be x=0, 1, . . . , ND−

1 in serial order, letting the index of the inner code be y =0, 1, . . . , NA−

1 in serial order, letting the x-th block of the y-th inner code be (x, y), and letting k he a variable that counts the number of blocks to he inputted, with respect to the range of the ND×

NB×

NA bits, the second deinterleaver inputs blocks (x, y) represented by

x=(k mod ND)

y=(k mod NA)

k=0,1,2, . . . , N−

1 in order, and outputs them in ascending order of the index of the blocks, from the inner code with the smallest index.

17. The data processing apparatus according to claim 12, wherein the first deinterleaver processes in serial order NB blocks by NB blocks with NA bits as one block, and outputting, within a range of the NB blocks, the first bit of each of the blocks in order, then outputting the second bit of each of the blocks in order, thereafter repeating the same processing, and lastly, outputting the NA-th bit of each of the blocks in order.

18. The data processing apparatus according to claim 12, wherein a cycle of the interleaving is smaller than one codeword of the product code.

19. A data processing method performed by a data processing apparatus that includes a program that processes data read from a recording medium on which the data is recorded, the data being obtained by performing interleaving on a product code encoded in the e order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with n bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits, the data processing method comprising steps of:

performing deinterleaving on data to rearrange the data into an original order, the data being read from the recording medium and subjected to the interleaving so that in a recording order after the interleaving is performed, the same codeword of the inner code is not included in i consecutive bits, and j (j>

i) consecutive bits do not span a plurality of symbols of the same codeword of the outer code, i representing the number of pieces of the inner codes included in one product code and j representing a predetermined integral multiple of the product of i and n.

20. A non-transitory storage medium storing an executable program for causing a data processing apparatus to execute processing, the data processing apparatus processing data read from a recording medium on which the data is recorded, the data being obtained by performing interleaving on a product code encoded in the order of an outer code and an inner code by using, as the outer code, a code that performs error correction in units of symbols with n bits as one symbol, and using, as the inner code, a code that performs error correction in units of bits, the data processing method comprising the steps of:

performing deinterleaving on data to rearrange the data into an original order, the data being read from the recording medium and subjected to the interleaving so that in a recording order after the interleaving is performed, the same codeword of the inner code is not included in i consecutive bits, and j (j>

i) consecutive bits do not span a plurality of symbols of the same codeword of the outer code, i representing;

the number of pieces of the inner codes included in one product code and j representing a predetermined integral multiple of the product of i and n.