Model for a hardware device-independent method of defining embedded firmware for programmable systems

• US 8,539,398 B2
• Filed: 05/27/2010
• Issued: 09/17/2013
• Est. Priority Date: 08/13/2004
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: McDonald, John, Pearson, Jon, Ogami, Kenneth, Anderson, Doug
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US12/789,399
• Publication Number:
  US 20100275173A1
• Time in Patent Office: 1,209 Days
• Field of Search: 716138-139, 716100-102, 716116-117
• US Class Current: 716/100
• CPC Class Codes: G06F 8/38 for implementing user interfaces

Abstract

A processing device programming system automatically provides a user interface comprising a selectable list of one or more processing devices based on a system level solution, automatically generates an embedded programmable system solution from the system level solution and a processing device selected from the selectable list of one or more processing devices, and automatically programs the processing device according to the embedded programmable system solution.

Claims

1. A system, comprising:

at least one processor configured to;

generate a selectable list of a plurality of processing devices based on a previously-created device-independent system-level solution;

validate at least one of the plurality of processing devices by determining which of the plurality of processing devices can be programmed according to a current state of the device-independent system-level solution;

generate an embedded programmable system solution from the device- independent system-level solution and a processing device selected from the selectable list of the plurality of processing devices;

generate a programming image file based on the embedded programmable system solution;

save a first file comprising the device-independent system-level solution; and

generate a schematic of the programmed selected processing device.

2. The system of claim 1, wherein the selectable list of the plurality of processing devices comprises at least one of a programmable logic device, a field programmable gate array, a microcontroller, a microprocessor-based device, and a circuit comprising a processing device.

3. The system of claim 1, comprising:

a video display unit, wherein the video display unit is coupled to the at least one processor.

4. The system of claim 3, wherein the at least one processor is configured to generate a graphical user interface on the video display unit, wherein the selectable list of the plurality of processing devices is provided to the user through the graphical user interface.

5. The system of claim 3, wherein the at least one processor is configured to delete one or more lower level files associated with the embedded programmable system.

6. The system of claim 3, wherein the at least one processor is configured to match resource requirements of one or more functions of the device-independent system-level solution to one or more base projects associated with the plurality of processing devices to determine the selectable list of the plurality of processing devices.

7. The system of claim 6, wherein the at least one processor is configured to generate one or more base projects associated with the the plurality of processing devices based upon the resource requirements of the one or more functions of the device-independent system-level solution and physical parameters associated with the the plurality of processing devices.

8. The system of claim 3, wherein the at least one processor is configured to provide to the user a selectable list of a plurality of high level devices to design the device-independent system-level solution.

9. The system of claim 8, wherein the at least one processor is configured to update the selectable list of the plurality of high level devices and the selectable list of the the plurality of processing devices in response to a selection of high level device from the plurality of high level devices.

10. The system of claim 9, wherein the at least one processor is configured to validate a current state of the device-independent system-level solution.

11. The system of claim 10, wherein the at least one processor is configured to validate executable expressions associated with the selected high level devices.

12. The system of claim 1, wherein the schematic comprises at least one of functional pins, input output devices, and interfacing circuitry.

13. A method, comprising:

selecting a processing device from a selectable list of one or more processing devices based on a previously-created device-independent system-level solution, wherein the selectable list of one or more processing devices is generated on a video display unit;

validating a current state of the device-independent system-level solution;

validating executable expressions associated with selected high level devices;

validating the one or more processing devices by matching resources required by the current state of the device-independent system-level solution to the one or more processing devices;

automatically generating an embedded programmable system solution from the device-independent system-level solution and the selected processing device; and

automatically generating a programming image file based on the embedded programmable system solution.

14. The method of claim 13, wherein the selectable list of one or more processing devices comprises at least one of a programmable logic device, a field programmable gate array, a microcontroller, a microprocessor-based device, and a circuit comprising a processing device.

15. The method of claim 13, comprising:

automatically providing the selectable list of one or more processing devices to a user.

16. The method of claim 13, comprising:

automatically matching resource requirements of one or more functions of the device-independent system-level solution to one or more base projects associated with the one or more processing devices to determine the selectable list of one or more processing devices.

17. The method of claim 16, comprising:

automatically generating the one or more base projects associated with the one or more processing devices based upon the resource requirements of the one or more functions of the device-independent system-level solution and physical parameters associated with the one or more processing devices.

18. The method of claim 13, comprising:

automatically providing to the user a selectable list of a plurality of high level devices to design the device-independent system-level solution.

19. The method of claim 18, comprising:

updating the selectable list of the plurality of high level devices and the selectable list of the one or more processing devices in response to a selection of a high level device from the plurality of high level devices.