Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method

• US 8,539,419 B2
• Filed: 03/15/2012
• Issued: 09/17/2013
• Est. Priority Date: 07/27/2009
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Rao, Vishwas M., Parker, James C.
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/421,710
• Publication Number:
  US 20120174048A1
• Time in Patent Office: 551 Days
• Field of Search: 716/110, 716/113, 716118-119, 716/122, 716124-125
• US Class Current: 716/122
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

Methods of designing an IC and a hierarchical design flow generator are disclosed. In one embodiment, the method includes: (1) receiving timing and physical constraints for an IC design at an apparatus, (2) establishing a hierarchical design flow for providing an implementation of the IC design employing the apparatus and (3) partitioning the hierarchical design flow into a late design flow portion and an early design flow portion employing the apparatus, wherein the late design flow portion is substantially the same for different design flow methodologies.

Claims

1. A method of designing an integrated circuit, comprising:

receiving timing constraints for an integrated circuit design at an apparatus;

establishing a hierarchical design flow employing said timing constraints for providing an implementation of said integrated circuit design;

partitioning said hierarchical design flow into a late design flow portion and an early design flow portion employing said apparatus, wherein said late design flow portion is substantially the same for different design flow methodologies.

2. The method as recited in claim 1 wherein said portioning into said early design flow portion and said late design flow portion allow simultaneous top-down and bottom-up design methodologies for said integrated circuit design.

3. The method as recited in claim 1 wherein said early design flow portion includes establishing an early timing budget based on achievable input and output constraints from a bottom-up block-flow of said early design flow portion.

4. The method as recited in claim 3 wherein said early design flow portion includes employing said early timing budget to generate an early top-level implementation and an early block level implementation of said integrated circuit design.

5. The method as recited in claim 4 wherein said late design flow portion includes generating a final block level implementation based on said early block level implementation.

6. The method as recited in claim 5 wherein said late design flow portion includes establishing a final timing budget based on said early top-level implementation and said generating said final block level implementation.

7. The method as recited in claim 6 wherein said late design flow portion includes providing a final top-level implementation of said integrated circuit design employing said final timing budget and said final block level implementation.

8. The method as recited in claim 7 further comprising constructing said integrated circuit based on said final top-level implementation.

9. The method as recited in claim 1 further comprising receiving physical constraints for said integrated circuit design at said apparatus and establishing said hierarchical design flow employing said physical constraints.