Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics

• US 8,539,423 B2
• Filed: 10/11/2012
• Issued: 09/17/2013
• Est. Priority Date: 05/07/2008
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Jamann, Joseph J., Parker, James C., Rao, Vishwas M.
• Primary Examiner(s): LEVIN, NAUM B
• Application Number:
  US13/649,996
• Publication Number:
  US 20130104096A1
• Time in Patent Office: 341 Days
• Field of Search: 716132-136
• US Class Current: 716/133
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

One aspect provides a method of designing an integrated circuit. In one embodiment, the method includes: (1) generating a functional design for the integrated circuit, (2) determining performance objectives for the integrated circuit, (3) determining an optimization target voltage for the integrated circuit, (4) determining whether the integrated circuit needs voltage scaling to achieve the performance objectives at the optimization target voltage and, if so, whether the integrated circuit is to employ static voltage scaling or adaptive voltage scaling, (5) using the optimization target voltage to synthesize a layout from the functional integrated circuit design that meets the performance objectives by employing standardized data created by designing at least one representative benchmark circuit, and (6) performing a timing signoff of the layout at the optimization target voltage.

Claims

1. A method of designing an integrated circuit, comprising:

generating, using a computer, a functional design for said integrated circuit;

determining performance objectives for said integrated circuit;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, whether said integrated circuit is to employ static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a layout from said functional integrated circuit design that meets said performance objectives by employing standardized data created by designing at least one representative benchmark circuit, establishing standard sensitization and measurement rules for delay and power for said at least one representative benchmark circuit and across corners in said technology nodes, performing a simulation by sweeping through a range of values and at predetermined intervals across said corners, extracting data from said simulation, and parsing and interpreting said data to produce at least one report; and

performing a timing signoff of said layout at said optimization target voltage.

2. The method as recited in claim 1 wherein said using comprises:

using said optimization target voltage to synthesize a netlist from said functional integrated circuit design that meets said performance objectives; and

generating a layout of said integrated circuit from said netlist.

3. The method as recited in claim 1 wherein said performance objectives include one selected from the group consisting of:

a target power consumption,

a target area, and

a target speed.

4. The method as recited in claim 1 wherein said using comprises:

synthesizing a clock tree for said integrated circuit; and

determining a routing at said optimization target voltage.

5. The method as recited in claim 1 wherein said determining whether said integrated circuit needs said voltage scaling is carried out with respect to more than one fabrication technology, said performance/power ratio being unitless.

6. The method as recited in claim 1 wherein said adaptive voltage scaling is capable of being carried out without software control.

7. The method as recited in claim 1 wherein said using comprises decreasing an area of a safe zone associated with said integrated circuit.

8. A method of designing an integrated circuit, comprising:

generating, using a computer, a functional design for said integrated circuit;

determining performance objectives for said integrated circuit;

determining an optimization target voltage for said integrated circuit;

determining whether said integrated circuit needs voltage scaling to achieve said performance objectives at said optimization target voltage and, if so, whether said integrated circuit is to employ static voltage scaling or adaptive voltage scaling;

using said optimization target voltage to synthesize a layout from said functional integrated circuit design that meets said performance objectives by employing standardized data created by designing at least one representative benchmark circuit; and

performing a timing signoff of said layout at said optimization target voltage.

9. The method as recited in claim 8 wherein using said optimization target voltage to synthesize said layout includes establishing standard sensitization and measurement rules for delay and power for said at least one representative benchmark circuit and across corners in technology nodes considered for said functional integrated circuit design.

10. The method as recited in claim 8 wherein using said optimization target voltage to synthesize said layout includes performing a simulation by sweeping through a range of values and at predetermined intervals across corners, extracting data from said simulation, and parsing and interpreting said data to produce at least one report.