Accelerating data transfer in a virtual computer system with tightly coupled TCP connections

• US 8,539,513 B1
• Filed: 03/24/2009
• Issued: 09/17/2013
• Est. Priority Date: 04/01/2008
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Starr, Daryl D., Craft, Peter K., Philbrick, Clive M.
• Primary Examiner(s): Sough, H S
• Assistant Examiner(s): SEYE, ABDOU K
• Application Number:
  US12/410,366
• Time in Patent Office: 1,638 Days
• Field of Search: 719/319
• US Class Current: 719/319
• CPC Class Codes: G06F 2009/45595 Network integration; Enabling network access in virtual machine instances
• CPC Class Codes: G06F 9/45533 Hypervisors; Virtual machine monitors
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/54 Interprogram communication

Abstract

First and second operating systems of a virtual computer system can communicate using respective first and second network protocol stacks, by employing procedures that are specialized for a situation in which a TCP control block of the first stack and a TCP control block of the second stack correspond to the same logical connection. In this case, various TCP requirements can be bypassed by coupling the TCP control blocks, reducing or eliminating data copies and providing other efficiencies.

Claims

1. A device comprising:

a first operating system running on a computer system, the first operating system having a first network protocol stack including a first transmission control protocol (TCP) layer;

a second operating system running on the computer system, the second operating system having a second network protocol stack including a second TCP layer;

a logical connection established between the first and second TCP layers, the logical connection represented by the first TCP layer as a first TCP control block, the logical connection represented by the second TCP layer as a second TCP control block;

wherein the first TCP control block is coupled to the second TCP control block by a processor that accesses the first and second TCP control blocks and runs instructions that are specialized for a situation in which the first and second TCP control blocks correspond to the same logical connection.

2. The method of claim 1, wherein executing instructions includes referencing the first TCP control block and the second TCP control block within a function call.

3. The device of claim 1, wherein the processor is a part of an interface that is connected to the computer system by an input/output (I/0) channel.

4. The device of claim 1, wherein the instructions are a part of a virtual machine manager.

5. The device of claim 1, wherein the instructions are a part of the first operating system.

6. The device of claim 1, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block and the second TCP control block correspond to the same logical connection.

7. The device of claim 1, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block and the second TCP control block are reciprocal to each other.

8. The device of claim 1, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block is identified by IP addresses and TCP ports that are a mirror image of the IP addresses and TCP ports of the second TCP control block.

9. The device of claim 1, further comprising an instruction, stored on a computer readable medium, to flag the first TCP control block and the second TCP control block as tightly-coupled.

10. The device of claim 1, wherein the first TCP control block points to a location in memory of the second TCP control block, and the second TCP control block points to a location in memory of the first TCP control block.

11. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data without a corresponding TCP header from a memory source controlled by a process running above the first TCP layer directly to a memory destination controlled by a process running above the second TCP layer.

12. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data by direct memory access (DMA) from a memory source controlled by a process running above the first TCP layer to a memory destination controlled by a process running above the second TCP layer.

13. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data without transferring window update packets between the first and second TCP layers.

14. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data without transferring acknowledgements (ACKs) between the first and second TCP layers.

15. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data without segmenting data that is transferred between the first and second TCP layers.

16. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to transfer data without checksumming data that is transferred between the first and second TCP layers.

17. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to substantially simultaneously reference the first and second TCP control blocks by the processor.

18. The device of claim 1, wherein the instructions include an instruction, stored on a computer readable medium, to substantially simultaneously update the first and second TCP control blocks by the processor.

19. The device of claim 1, wherein:

the first operating system runs on a first central processing unit (CPU);

the second operating system runs on a second CPU that is connected to the first CPU by an I/0 channel.

20. A device comprising:

a first operating system running on a computer system, the first operating system having a first network protocol stack including a first transmission control protocol (TCP) layer;

a second operating system running on the computer system, the second operating system having a second network protocol stack including a second TCP layer;

a logical connection established between the first and second TCP layers, the logical connection represented by the first TCP layer as a first TCP control block, the logical connection represented by the second TCP layer as a second TCP control block; and

a processor executing a function call that references the first and second TCP control blocks.

21. The device of claim 20, wherein:

the first operating system runs on a first central processing unit (CPU); and

the second operating system runs on a second CPU that is connected to the first CPU by an 1/0 channel.

22. The device of claim 20, wherein the processor is a part of an interface that is connected to the computer system by an input/output (1/0) channel.

23. The device of claim 20, wherein the instructions are a part of a virtual machine manager.

24. The device of claim 20, wherein the instructions are a part of the first operating system.

25. The device of claim 20, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block and the second TCP control block correspond to the same logical connection.

26. The device of claim 20, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block and the second TCP control block are reciprocal to each other.

27. The device of claim 20, further comprising an instruction, stored on a computer readable medium, to check whether the first TCP control block is identified by IP addresses and TCP ports that are a mirror image of the IP addresses and TCP ports of the second TCP control block.

28. The device of claim 20, further comprising an instruction, stored on a computer readable medium, to flag the first TCP control block and the second TCP control block as tightly-coupled.

29. The device of claim 20, wherein the first TCP control block points to a location in memory of the second TCP control block, and the second TCP control block points to a location in memory of the first TCP control block.

30. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data without a corresponding TCP header from a memory source controlled by a process running above the first TCP layer directly to a memory destination controlled by a process running above the second TCP layer.

31. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data by direct memory access (DMA) from a memory source controlled by a process running above the first TCP layer to a memory destination controlled by a process running above the second TCP layer.

32. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data without transferring window update packets between the first and second TCP layers.

33. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data without transferring acknowledgements (ACKs) between the first and second TCP layers.

34. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data without segmenting the data that is transferred between the first and second TCP layers.

35. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to transfer data without checksumming the data that is transferred between the first and second TCP layers.

36. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to substantially simultaneously reference the first and second TCP control blocks by the processor.

37. The device of claim 20, wherein the function call includes an instruction, stored on a computer readable medium, to substantially simultaneously update the first and second TCP control blocks by the processor.

38. A device comprising:

a computer readable memory;

a first control block (CB) stored in the memory and identified by a first CB source IP address, a first CB destination IP address, a first CB source TCP port and a first CB destination TCP port;

a second CB stored in the memory and identified by a second CB source IP address, a second CB destination IP address, a second CB source TCP port and a second CB destination TCP port, wherein the second CB source IP address is the first CB destination IP address, the second CB destination IP address is the first CB source IP address, the second CB source TCP port is the first CB destination TCP port, and the second CB destination TCP port is the first CB source TCP port; and

a function call stored in the memory and referencing the first CB and the second CB.