Thin film transistor, method of manufacturing the same and flat panel display device having the same

• US 8,541,258 B2
• Filed: 04/21/2011
• Issued: 09/24/2013
• Est. Priority Date: 06/30/2008
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Min-Kyu, Jeong, Jong-Han, Ahn, Tae-Kyung, Jeong, Jae-Kyeong, Mo, Yeon-Gon, Park, Jin-Seong, Chung, Hyun-Joong, Kim, Kwang-Suk, Yang, Hui-Won
• Primary Examiner(s): Pham, Long
• Application Number:
  US13/091,614
• Publication Number:
  US 20110193083A1
• Time in Patent Office: 887 Days
• Field of Search: 438/104, 438/149, 438/158
• US Class Current: 438/104
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT) using an oxide semiconductor as an active layer, a method of manufacturing the TFT, and a flat panel display device having the TFT include source and drain electrodes formed on a substrate; an active layer formed of an oxide semiconductor disposed on the source and drain electrodes; a gate electrode; and an interfacial stability layer formed on at least one of top and bottom surfaces of the active layer. In the TFT, the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV. Since the interfacial stability layer has the same characteristics as a gate insulating layer and a passivation layer, chemically high interface stability is maintained. Since the interfacial stability layer has a band gap equal to or greater than that of the active layer, charge trapping is physically prevented.

Claims

1. A method of manufacturing a thin film transistor, comprising:

forming source and drain electrodes on a substrate;

sequentially forming a first interfacial stability layer and an oxide semiconductor layer on the substrate having the source and drain electrodes;

patterning the oxide semiconductor layer to form an active layer;

forming a gate insulating layer on the substrate to cover the active layer; and

forming a gate electrode on the gate insulating layer above the active layer, wherein the first interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV, and a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer.

2. The method of claim 1, wherein the first interfacial stability layer comprises one selected from the group consisting of SiO_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

3. The method of claim 1, wherein the first interfacial stability layer is formed using a physical deposition method.

4. The method of claim 1, wherein the first interfacial stability layer is formed to a thickness of 10 to 20 Å

.

5. The method of claim 1, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

6. The method of claim 5, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

7. The method of claim 1, wherein the first interfacial stability layer is patterned in the forming the active layer.

8. The method of claim 1, further comprising forming a second interfacial stability layer on the active layer opposite the first interfacial stability layer.

9. The method of claim 8, wherein the second interfacial stability layer comprises one selected from the group consisting of SiOx, SiOxNy, SiOxCy, SiOxCyHz, SiOxFy, GeOx, GdOx, AlOx, GaOx, SbO, ZrOx, HfOx, TaOx, YOx, VOx, MgOx, CaOx, BaOx, SrOx and SOG.

10. The method of claim 9, wherein the second interfacial stability layer is formed using a physical deposition method.

11. The method of claim 8, wherein the second interfacial stability layer is formed to a thickness of 50 to 5000 Å

.

12. A method of manufacturing a thin film transistor, comprising:

forming source and drain electrodes on a substrate;

sequentially forming an oxide semiconductor layer and an interfacial stability layer on the substrate having the source and drain electrodes;

patterning the interfacial stability layer and the oxide semiconductor layer to form an active layer;

forming a gate insulating layer on the substrate having the active layer; and

forming a gate electrode on the gate insulating layer above the active layer,

wherein the interfacial stability layer is formed of an oxide having a band gap of 3.0 to 8.0 eV, and a portion of the interfacial stability layer is disposed between the source and drain electrodes and the active layer.

13. The method of claim 12, wherein the oxide semiconductor layer comprises zinc oxide (ZnO).

14. The method of claim 13, wherein the oxide semiconductor layer is doped with at least one ion of gallium (Ga), indium (In), tin (Sn), zirconium (Zr), hafnium (Hf), cadmium (Cd), silver (Ag), copper (Cu), germanium (Ge), gadolinium (Gd), and vanadium (V).

15. The method of claim 12, wherein the interfacial stability layer comprises one selected from the group consisting of SiO_x, SiO_xN_y, SiO_xC_y, SiO_xC_yH_z, SiO_xF_y, GeO_x, GdO_x, AlO_x, GaO_x, SbO, ZrO_x, HfO_x, TaO_x, YO_x, VO_x, MgO_x, CaO_x, BaO_x, SrO_x, and SOG.

16. The method of claim 12, wherein the interfacial stability layer is formed using a physical deposition method.

17. The method of claim 12, wherein the interfacial stability layer is formed to a thickness of 50 to 5000 Å

.