Electronic device including a trench with a facet and a conductive structure therein and a process of forming the same

• US 8,541,302 B2
• Filed: 12/15/2011
• Issued: 09/24/2013
• Est. Priority Date: 12/15/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Loechelt, Gary H., Grivna, Gordon M.
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US13/327,454
• Publication Number:
  US 20130153988A1
• Time in Patent Office: 649 Days
• Field of Search: 438/212, 438/270, 257/329, 257/622, 257/623, 257/627
• US Class Current: 438/622
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An electronic device can include a transistor structure including a semiconductor layer overlying a substrate and a trench extending into the semiconductor layer having a tapered shape. In an embodiment, the tapered shape includes a facet. The transistor structure can include a source region and a drain region wherein different portions of the drain regions are disposed adjacent to the primary surface and within the trench. In another embodiment, different facets may be spaced apart from each other. Processes of forming the tapered etch can be tailored based on the needs or desires of a fabricator.

Claims

1. An electronic device comprising a transistor structure, comprising:

a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;

a trench extending into the semiconductor layer having a tapered shape, wherein the tapered shape includes a facet that lies substantially along a second plane that intersects the first plane at an angle in a range of approximately 20°

to approximately 70°

;

a source region of the transistor structure; and

a drain region of the transistor structure,

wherein;

portions of the source and drain regions are disposed adjacent to the primary surface; and

another portion of the drain region is disposed within the trench.

2. The electronic device of claim 1, wherein the transistor structure comprises:

a channel region disposed between the source and drain regions, wherein the channel region is disposed along the primary surface of the semiconductor layer; and

a gate electrode overlying the channel region, wherein substantially all of the gate electrode is disposed at an elevation above the primary surface.

3. The electronic device of claim 1, wherein the drain region comprises:

a doped semiconductor region adjacent to a tapered portion of the trench, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and

a conductive structure disposed within another portion of the trench below the tapered portion, wherein the other portion has a substantially vertical sidewall.

4. The electronic device of claim 3, further comprising an underlying doped region and a drain terminal, wherein:

the semiconductor layer is disposed over the underlying doped region;

the conductive structure is electrically connected to the doped semiconductor region and the underlying doped region; and

the underlying doped region is coupled to the drain terminal.

5. An electronic device comprising:

a semiconductor layer overlying a substrate and having a primary surface; and

a trench extending into the semiconductor layer and having a first facet and a second facet spaced apart from the second facet, wherein;

the first facet is disposed closer to the primary surface as compared to the second facet;

the first facet lies along a first plane, the second facet lies along a second plane, and the primary surface generally corresponds to a third plane; and

each of the first and second planes intersects the third plane at an angle in a range of approximately 20°

to approximately 70°

.

6. The electronic device of claim 5, wherein substantially all of the first facet is disposed at an elevation higher than substantially all of the second facet.

7. The electronic device of claim 5, wherein the trench has a substantially vertical sidewall between the first and second facets.

8. The electronic device of claim 7, further comprising another substantially vertical sidewall disposed below the second facet.

9. The electronic device of claim 7, further comprising:

a doped semiconductor region including a first portion adjacent to the first facet and a second portion adjacent to the second facet, wherein a dopant concentration of the doped semiconductor region is greater than a dopant concentration of the semiconductor layer at a location adjacent to the primary surface; and

a conductive electrode extending into the trench such that a lowest elevation of the conductive electrode within the trench is below a highest elevation of the second facet.

10. The electronic device of claim 9, further comprising:

a first insulating layer disposed between the first portion of the doped semiconductor region and the conductive electrode; and

a second insulating layer disposed between the second portion of the doped semiconductor region and the conductive electrode, wherein the second insulating layer is thicker than the first insulating layer.

11. A process of forming an electronic device comprising:

providing a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;

patterning a semiconductor layer to define a trench; and

forming a facet from a portion of the semiconductor layer, wherein the facet lies along a second plane that intersects the first plane at an angle in a range of approximately 20°

to approximately 70°

,

wherein in a finished device;

the facet is spaced apart from a bottom of the trench; and

as compared to a bottom of the trench, a lowest elevation of the facet is disposed closer to the primary surface.

12. The process of claim 11, wherein forming the facet comprises sputter etching the semiconductor layer.

13. The process of claim 11, further comprising forming a patterned resist layer over the semiconductor layer, wherein forming the facet comprises:

anisotropically etching the semiconductor layer; and

eroding the resist layer during anisotropically etching the semiconductor layer.

14. The process of claim 11, wherein forming the facet comprises wet etching the semiconductor layer with an etchant that preferentially etches along a crystal plane that is within approximately 10°

of the second plane.

15. The process of claim 14, wherein the etchant comprises a hydroxide and an alcohol.

16. The process of claim 11, wherein forming the facet is performed after patterning the semiconductor layer.

17. The process of claim 11, wherein patterning the semiconductor layer is performed after forming the facet.