Method for fixing an electronic component on a printed circuit board and system comprising a printed circuit board and at least one electronic component

• US 8,541,690 B2
• Filed: 05/15/2007
• Issued: 09/24/2013
• Est. Priority Date: 05/16/2006
• Status: Active Grant

• Current Assignee: AT&S Austria Technologie & Systemtechnik AG
• Original Assignee: AT&S Austria Technologie & Systemtechnik AG
• Inventors: Voraberger, Hannes, Riester, Markus, Stahr, Johannes, Schmid, Gerhard
• Primary Examiner(s): Thompson, Timothy
• Assistant Examiner(s): MILAKOVICH, NATHAN J
• Application Number:
  US12/227,364
• Publication Number:
  US 20090101398A1
• Time in Patent Office: 2,324 Days
• Field of Search: 174/260
• US Class Current: 174/260
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/498 Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers shape of the substrate H01L23/13
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01061 Promethium [Pm]
• CPC Class Codes: H01L 2924/01068 Erbium [Er]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/113 : Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/09436 : Pads or lands on permanent coating which covers the other conductors
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/005 : Punching of holes
• CPC Class Codes: H05K 3/107 : by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/465 : by applying an insulating layer having channels for the next circuit layer
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A method for fixing an electronic component on a printed circuit board, and contact-connecting the electronic component to the printed circuit board, the following steps are provided:—providing the printed circuit board having a plurality of contact and connection pads,—providing the electronic component having a number of contact and connection locations corresponding to the plurality of contact and connection pads, with a mutual spacing reduced in comparison with the spacing of the contact and connection pads, and—arranging or forming at least one interlayer for routing the contact and connection locations of the electronic component between the contact and connection pads and the contact and connection locations of the electronic component. A method for producing an interlayer for routing and a system having a printed circuit board and an electronic component using the interlayer for routing are also provided.

Claims

1. A process for attaching an electronic component on a circuit board or contacting the electronic component with the circuit board, comprising the steps of:

providing the circuit board with a plurality of contact or connection surfaces;

providing the electronic component with a number of contact or connection sites corresponding to the plurality of contact or connection surfaces of the circuit board, at mutual distances reduced relative to the distances of the contact or connection surfaces of the circuit board; and

forming between the contact or connection surfaces of the circuit board and the contact or connection sites of the electronic component at least one intermediate layer for disentangling the contact or connection sites of the electronic component;

wherein, after the structuring of the intermediate layer, an additional support layer for the attachment or contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component;

wherein the additional support layer covers both the intermediate layer and portions of the circuit board;

wherein the intermediate layer is merely formed in the region of the contact or connection surfaces of the circuit board as well as the contact or connection sites of the electronic component; and

wherein the intermediate layer is created as a part of a substrate of the circuit board by adding a layer to the circuit board.

2. The process according to claim 1, wherein the intermediate layer is formed with conductive tracks or structures between contact zones corresponding to the contact or connection sites of the electronic component and corresponding to the contact or connection surfaces of the circuit board.

3. The process according to claim 1, wherein contacting between the contact or connection sites of the electronic component and the intermediate layer is effected via contacts of the electronic component.

4. The process according to claim 1, wherein contact or connection sites of the electronic component are directly contacted with contact zones of the intermediate layer.

5. The process according to claim 1, wherein the electronic component is attached on the circuit board with contact or connection sites oriented away from the circuit board, and is overlaid by the intermediate layer for disentanglement and connection to the contact or connection surfaces of the circuit board.

6. A process for producing an intermediate layer for disentangling contact or connection sites of an electronic component from contact or connection surfaces of a circuit board, comprising the steps of:

providing the circuit board with a plurality of contact or connection surfaces;

forming a base material of the intermediate layer merely in the region of the contact or connection surfaces of the circuit board;

structuring the intermediate layer to form conductive tracks or structures and contact sites for contacting with contact or connection surfaces of the circuit board and with contact or connection sites of an electronic component to be attached on the circuit board;

wherein, after the structuring of the intermediate layer, an additional support layer for the attachment or contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component;

wherein the additional support layer covers both the intermediate layer and portions of the circuit board; and

wherein the intermediate layer is created as a part of a substrate of the circuit board by adding a layer to the circuit board.

7. The process according to claim 6, wherein the structuring of the intermediate layer is performed by subtractive techniques, semi-additive techniques, additive techniques or embossing techniques or laser structuring techniques.

8. The process according to claim 6, wherein the intermediate layer is formed with a thickness reduced relative to the thickness of a circuit board layer.

9. The process according to claim 8, wherein the thickness of the intermediate layer is selected to be less than half, in particular less than a third, of the thickness of a circuit board layer.

10. The process according to claim 6, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are selected to be less than 50 μ

m.

11. The process according to claim 6, wherein the intermediate layer is used as a support or enclosure for the electronic component.

19. The process according to claim 6, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are selected to be less than 30 μ

m.

12. A system including a circuit board and at least one electronic component, wherein at least one intermediate layer for the disentanglement of contact or connection sites of the electronic component from contact or connection surfaces of the circuit board is formed between the contact or connection sites of the electronic component and the contact or connection surfaces of the circuit board, and that the contact or connection sites of the electronic component comprise mutual distances reduced relative to the contact or connection sites of the circuit board;

wherein an additional support layer for the attachment and contacting of the electronic component is applied on the intermediate layer for disentanglement and provided with contacts for the electronic component;

wherein the intermediate layer is merely formed in the region of the contact or connection surfaces of the circuit board as well as the contact or connection sites of the electronic component;

wherein the additional support layer covers both the intermediate layer and portions of the circuit board; and

wherein the intermediate layer is created as part of a substrate of the circuit board by adding a layer to the circuit board.

13. The system according to claim 12, wherein the intermediate layer is formed with conductive tracks or structures between contact zones corresponding to the contact or connection sites of the electronic component and corresponding to the contact or connection surfaces of the circuit board.

14. The system according to claim 12, wherein the intermediate layer is formed with a thickness reduced relative to the thickness of a circuit board layer.

15. The system according to claim 14, wherein the thickness of the intermediate layer amounts to less than half of the thickness of a circuit board layer.

16. The system according to claim 12, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are less than 50 μ

m.

17. The system according to claim 12, wherein the intermediate layer is used as a support or enclosure for the electronic component.

18. The system according to claim 12, wherein the circuit board is formed with a plurality of superimposed circuit board layers which are at least partially interconnected by conductive passages or microvias connecting individual circuit board layers.

20. The system according to claim 14, wherein the thickness of the intermediate layer amounts to less than a third of the thickness of a circuit board layer.

21. The system according to claim 12, wherein the intermediate layer is provided with conductive tracks or conductive structures whose widths are less than 30 μ

m.