Semiconductor device and structure

• US 8,541,819 B1
• Filed: 12/09/2010
• Issued: 09/24/2013
• Est. Priority Date: 12/09/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk, Sekar, Deepak C.
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US12/963,659
• Time in Patent Office: 1,020 Days
• Field of Search: 257/211, 257/758, 257/773, 257/775, 257/E23.011, 257/E23.079, 257/E23.145, 257/E23.151, 257/E23.152
• US Class Current: 257/211
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12032 Schottky diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15788 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 41/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/20 : characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 63/30 : comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/845 : the switching components being connected to a common vertical conductor

Abstract

A semiconductor device including: a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between; where the at least one conductive layer includes a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and where the second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of the first conductive layer, and the second conductive layer current carrying capacity being greater than the current carrying capacity of the third conductive layer.

Claims

1. A semiconductor device comprising:

a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between;

wherein

said at least one conductive layer comprises a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and wherein

said second conductive layer having a

predetermined second layer current carrying capacity greater than the current carrying capacity of said first conductive layer, and said second conductive layer current carrying capacity being greater than the current carrying capacity of said third conductive layer.

2. A device according to claim 1 wherein said at least one conductive layer comprises metal.

3. A device according to claim 1 wherein said at least one conductive layer comprises copper or aluminum.

4. A device according to claim 1 wherein said predetermined second layer current carrying capacity comprises higher layer thickness.

5. A device according to claim 1 wherein said predetermined second layer current carrying capacity comprises larger metal line width.

6. A device according to claim 1 wherein said mono-crystal comprises silicon.

7. A device according to claim 1 wherein said first mono-crystal and said second mono-crystal comprise two different crystalline materials.

8. A semiconductor device comprising:

a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between;

wherein

said at least one conductive layer comprises a first conductive layer overlaying a second conductive layer overlying a third conductive layer; and

wherein

said second conductive layer has a greater layer thickness than said first conductive layer, and said second conductive layer has a greater layer thickness than said third conductive layer.

9. A device according to claim 8 wherein said at least one conductive layer comprises metal.

10. A device according to claim 8 wherein said at least one conductive layer comprises copper or aluminum.

11. A device according to claim 8 wherein said greater layer thickness comprises larger metal line width.

12. A device according to claim 8 wherein said greater layer thickness comprises higher current carrying capability.

13. A device according to claim 8 wherein said mono-crystal comprises silicon.

14. A device according to claim 8 wherein said first mono-crystal and said second mono-crystal comprise two different crystalline materials.

15. A semiconductor device comprising:

a first mono-crystal layer and a second mono-crystal layer and at least one conductive layer in-between;

wherein

said at least one conductive layer comprises a first conductive layer overlaying a second conductive layer overlying a third conductive layer, and wherein

said second conductive layer having a predetermined second layer current carrying capacity greater than the current carrying capacity of said first conductive layer, and said second conductive layer current carrying capacity being greater than the current carrying capacity of said third conductive layer,

and wherein

said first mono-crystal layer comprises first transistors, and said second mono-crystal layer comprises second transistors, and wherein

said second transistors are aligned to said first transistors.

16. A semiconductor device according to claim 15 wherein said first mono-crystal and said second mono-crystal comprise two different crystalline materials.

17. A semiconductor device according to claim 15 wherein said first mono-crystal comprises silicon.

18. A semiconductor device according to claim 15 wherein

said first mono-crystal comprises silicon in first orientation, and wherein

said second mono-crystal comprises silicon with a different orientation than said first orientation.

19. A device according to claim 15 wherein said at least one conductive layer comprises copper or aluminum.

20. A device according to claim 15 wherein said predetermined second layer current carrying capacity comprises a higher layer thickness.