Noise shielding techniques for ultra low current measurements in biochemical applications

• US 8,541,849 B2
• Filed: 02/14/2012
• Issued: 09/24/2013
• Est. Priority Date: 02/14/2012
• Status: Active Grant

• Current Assignee: Roche Sequencing Solutions, Inc. (Roche Holding AG)
• Original Assignee: Genia Technologies, Inc. (Roche Holding AG)
• Inventors: Chen, Roger
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/396,522
• Publication Number:
  US 20130207205A1
• Time in Patent Office: 588 Days
• Field of Search: 257/414
• US Class Current: 257/414
• CPC Class Codes: B82Y 15/00 Nanotechnology for interacting, sensing or actuating, e.g. quantum dots as markers in protein assays or molecular motors
• CPC Class Codes: G01N 27/44756 Apparatus specially adapted therefor
• CPC Class Codes: G01N 27/44791 Microapparatus sample containers with integrated microfluidic structures B01L3/5027
• CPC Class Codes: G01N 33/48721 Investigating individual macromolecules, e.g. by translocation through nanopores Coulter counters in general G01N15/12; fabrication methods for nanoscale apertures B81B1/00; sequencing of nucleic acids C12Q1/68
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device having an integrated noise shield is disclosed. The device includes a plurality of vertical shielding structures substantially surrounding a semiconductor device. The device further includes an opening above the semiconductor device substantially filled with a conductive fluid, wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation. In some embodiments, the device further includes a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation. In some embodiments, the opening is configured to allow a biological sample to be introduced into the semiconductor device. In some embodiments, the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together. In some embodiments, the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.

Claims

1. A device having an integrated noise shield, comprising:

a plurality of vertical shielding structures substantially surrounding a semiconductor device; and

an opening above the semiconductor device substantially filled with a conductive fluid;

wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation.

2. The device of claim 1, further comprising a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation.

3. The device of claim 2, wherein the conductive bottom shield comprises a metal layer.

4. The device of claim 2, wherein the conductive bottom shield comprises a substrate layer.

5. The device of claim 1, wherein the opening is configured to allow a biological sample to be introduced into the semiconductor device.

6. The device of claim 1, wherein the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.

7. The device of claim 6, wherein the plurality of vias are arranged in a single concentric ring surrounding the semiconductor device.

8. The device of claim 6, wherein the plurality of vias are arranged in a plurality of concentric rings, and wherein the vias in a first ring of vias are offset from the vias in a second ring of vias.

9. The device of claim 1, wherein the conductive fluid comprises an electrolyte.

10. The device of claim 1, wherein the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.

11. The device of claim 1, further comprising a conductive layer forming a portion of the integrated noise shield, wherein the conductive layer is above the plurality of vertical shielding structures, and wherein the conductive layer is extended horizontally and radially outwards from the plurality of vertical shielding structures, shielding ambient radiation from passing through a plurality of gaps between the plurality of vertical shielding structures.

12. The device of claim 1, further comprising more than one conductive layers forming a portion of the integrated noise shield, and further comprising an oxide layer between the more than one conductive layers, and wherein the oxide layer is configured to form a capacitor.

13. The device of claim 1, further comprising an oxide layer insulating a conductive layer from the conductive fluid.

14. The device of claim 13, wherein the oxide layer is configured to form a capacitor.

15. A method for shielding a device from noise, comprising:

providing a plurality of vertical shielding structures substantially surrounding a semiconductor device; and

providing an opening above the semiconductor device substantially filled with a conductive fluid;

wherein the plurality of vertical shielding structures and the conductive fluid shield the semiconductor device from ambient radiation.

16. The method of claim 15, further comprising providing a conductive bottom shield below the semiconductor device shielding the semiconductor device from ambient radiation.

17. The method of claim 15, wherein the opening is configured to allow a biological sample to be introduced into the semiconductor device.

18. The method of claim 15, wherein the vertical shielding structures comprise a plurality of vias, wherein each of the plurality of vias connects more than one conductive layers together.

19. The method of claim 18, wherein the plurality of vias are arranged in a single concentric ring surrounding the semiconductor device.

20. The method of claim 18, wherein the plurality of vias are arranged in a plurality of concentric rings, and wherein the vias in a first ring of vias are offset from the vias in a second ring of vias.

21. The method of claim 15, wherein the conductive fluid comprises an electrolyte.

22. The method of claim 15, wherein the device comprises a nanopore device, and wherein the nanopore device comprises a single cell of a nanopore array.