Semiconductor device having shielded conductive vias

• US 8,541,883 B2
• Filed: 11/29/2011
• Issued: 09/24/2013
• Est. Priority Date: 11/29/2011
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Cheng, Hung-Hsiang, Wu, Chih-Wei, Lin, Tzu-Chih, Hung, Chang-Ying
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/306,762
• Publication Number:
  US 20130134601A1
• Time in Patent Office: 665 Days
• Field of Search: 257/686, 257773-774, 257/777, 438618-624, 438637-638, 438672-673
• US Class Current: 257/774
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

Abstract

The present invention relates to a semiconductor device having a shielding layer. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer.

Claims

1. A semiconductor device, comprising

a substrate composed of a semiconductor material;

a conductive via, the conductive via including

an inner conductive layer surrounding a central axis of a through hole in the substrate;

a metal shielding layer surrounding the inner conductive layer and disposed on a side wall of the through hole directly contacting the semiconductor material of the substrate; and

an insulation material disposed between the inner conductive layer and the shielding layer;

wherein the inner conductive layer and the shielding layer are ring structures substantially coaxial to the central axis; and

a first metal layer disposed on a first surface of the substrate, the first metal layer contacting the metal shielding layer.

2. The semiconductor device of claim 1, wherein the inner conductive layer surrounds a central portion.

3. The semiconductor device of claim 2, wherein the inner conductive layer is disposed on an outer peripheral surface of the central portion.

4. The semiconductor device of claim 2, wherein the central portion is made of a material different from the substrate.

5. The semiconductor device of claim 1, wherein the substrate further includes a central groove, an outer groove, and an isolation material, wherein the central groove is defined by the inner conductive layer, the outer groove surrounds the shielding layer, and the isolation material is disposed in the central groove and the outer groove.

6. The semiconductor device of claim 1, wherein the insulation material is one of polymer and air.

7. The semiconductor device of claim 1, wherein the metal layer is one of a ground plane and a power plane.

8. The semiconductor device of claim 1, further including:

a first passivation layer, disposed on the first metal layer and having a first opening to expose the inner conductive layer; and

a first redistribution layer, disposed in the first opening of the first passivation layer so as to contact the inner conductive layer.

9. The semiconductor device of claim 1, wherein the first metal layer has a plurality of openings which forms a mesh appearance.

10. A semiconductor device, comprising

a substrate;

a first conductive via including a shielding layer, a first inner conductive layer, and an insulation material, the shielding layer surrounding the first inner conductive layer, the first inner conductive layer surrounding a central axis of a first through hole in the substrate, and the insulation material disposed between the shielding layer and the first inner conductive layer;

a second conductive via including a second inner conductive layer, the second inner conductive via disposed on a sidewall of a second through hole in the substrate; and

a metal layer disposed on a surface of the substrate, the metal layer covering the second conductive via and contacting the shielding layer of the first conductive via and the second inner conductive layer of the second conductive via.

11. The semiconductor device of claim 10, wherein the first inner conductive layer and the shielding layer are ring structures substantially coaxial to the central axis of the first through hole.

12. The semiconductor device of claim 10, wherein the first inner conductive layer surrounds a central portion.

13. The semiconductor device of claim 10, further comprising:

a second metal layer, disposed on a second surface of the substrate and contacting the shielding layer.

14. The semiconductor of claim 10, further comprising:

a passivation layer, disposed on the metal layer and having a first opening to expose the first inner conductive layer and a second opening to expose part of the metal layer; and

a redistribution layer including a first redistribution portion and a second redistribution portion, the first redistribution portion, disposed in the first opening of the passivation layer so as to contact the first inner conductive layer and the second redistribution portion disposed in the second opening of the passivation layer so as to contact the metal layer.