Semiconductor device and driving method of the same

• US 8,542,004 B2
• Filed: 11/21/2012
• Issued: 09/24/2013
• Est. Priority Date: 02/12/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Inoue, Hiroki, Kato, Kiyoshi, Matsuzaki, Takanori, Nagatsuka, Shuhei
• Primary Examiner(s): Hollington, Jermele M
• Assistant Examiner(s): NGUYEN, TRUNG Q
• Application Number:
  US13/683,863
• Publication Number:
  US 20130077386A1
• Time in Patent Office: 307 Days
• Field of Search: None
• US Class Current: 324/76.11
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.

Claims

1. A semiconductor device comprising:

first to fifth lines;

a first multiplexer;

a second multiplexer; and

a memory cell,

the memory cell comprising;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and

a capacitor,

wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,

wherein the first line, the second source electrode, the first drain electrode, and a first terminal of the first multiplexer are electrically connected to each other,

wherein the second line, the first source electrode, and a first terminal of the second multiplexer are electrically connected to each other,

wherein the third line is electrically connected to a second terminal of the first multiplexer and a second terminal of the second multiplexer,

wherein the forth line is electrically connected to a third terminal of the first multiplexer, and

wherein the fifth line is electrically connected to a third terminal of the second multiplexer.

2. The semiconductor device according to claim 1,

wherein the first semiconductor is different from the second semiconductor.

3. The semiconductor device according to claim 1,

wherein the second semiconductor is an oxide semiconductor.

4. The semiconductor device according to claim 1, further comprising:

a write and read control signal line,

wherein the write and read control signal line is electrically connected to the first multiplexer and the second multiplexer.

5. The semiconductor device according to claim 1,

wherein the first gate electrode, the second drain electrode, and the one of electrodes of the capacitor are electrically connected to each other to form a node which holds charge.

6. The semiconductor device according to claim 1, further comprising:

a sixth line; and

a seventh line,

wherein the sixth line and the other of the electrodes of the capacitor are electrically connected to each other,

wherein the seventh line and the second gate electrode are electrically connected to each other.

7. A semiconductor device comprising:

first to fifth lines;

a potential change circuit; and

a memory cell,

the memory cell comprising;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and

a capacitor,

wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,

wherein the first line, the second source electrode, and the first drain electrode are electrically connected to each other,

wherein the second line and the first source electrode are electrically connected to each other,

wherein the potential change circuit is configured to select a first connection or a second connection,

wherein the first line and the second line are electrically connected to the third line when the first connection is selected, and

wherein the first line is electrically connected to the fourth line and the second line is electrically connected to the fifth line when the second connection is selected.

8. The semiconductor device according to claim 7,

wherein the first semiconductor is different from the second semiconductor.

9. The semiconductor device according to claim 7,

wherein the second semiconductor is an oxide semiconductor.

10. The semiconductor device according to claim 7, further comprising:

a write and read control signal line,

wherein the write and read control signal line is electrically connected to the potential change circuit.

11. The semiconductor device according to claim 7,

wherein the first gate electrode, the second drain electrode, and the one of electrodes of the capacitor are electrically connected to each other to form a node which holds charge.

12. The semiconductor device according to claim 7, further comprising:

a sixth line; and

a seventh line,

wherein the sixth line and the other of the electrodes of the capacitor are electrically connected to each other,

wherein the seventh line and the second gate electrode are electrically connected to each other.

13. A semiconductor device comprising:

a bit line;

a first source line;

an input signal line;

a read circuit input signal line;

a second source line;

a potential change circuit; and

a memory cell,

the memory cell comprising;

a first transistor comprising a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region including a first semiconductor;

a second transistor comprising a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region including a second semiconductor; and

a capacitor,

wherein the first gate electrode, the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,

wherein the bit line, the second source electrode, and the first drain electrode are electrically connected to each other,

wherein the first source line and the first source electrode are electrically connected to each other,

wherein the potential change circuit is configured to select a first connection or a second connection,

wherein the bit line and the first source line are electrically connected to the input signal line when the first connection is selected, and

wherein the bit line is electrically connected to the read circuit input signal line and the first source line is electrically connected to the second source line when the second connection is selected.

14. The semiconductor device according to claim 13,

wherein the first semiconductor is different from the second semiconductor.

15. The semiconductor device according to claim 13,

wherein the second semiconductor is an oxide semiconductor.

16. The semiconductor device according to claim 13, further comprising:

a write and read control signal line,

wherein the write and read control signal line is electrically connected to the potential change circuit.

17. The semiconductor device according to claim 13,

wherein the first gate electrode, the second drain electrode, and the one of electrodes of the capacitor are electrically connected to each other to form a node which holds charge.

18. The semiconductor device according to claim 13, further comprising:

a read word line; and

a write word line,

wherein the read word line and the other of the electrodes of the capacitor are electrically connected to each other,

wherein the write word line and the second gate electrode are electrically connected to each other.