Semiconductor device

• US 8,542,034 B2
• Filed: 05/16/2012
• Issued: 09/24/2013
• Est. Priority Date: 05/20/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US13/472,979
• Publication Number:
  US 20120293242A1
• Time in Patent Office: 496 Days
• Field of Search: 326/102, 326/82, 326/83, 326/36, 326/35, 326/11, 326/112, 326/119, 326/104, 326/38, 326/49, 327/109, 327/111, 327/409, 327/530
• US Class Current: 326/104
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/0944 using MOSFET or insulated gate field-effect transistors, i.e. IGFETH03K19/096 takes precedence

Abstract

As semiconductor devices including semiconductors, logic circuits are given. Logic circuits include dynamic logic circuits and static logic circuits and are formed using transistors and the like. Dynamic logic circuits can store data for a certain period of time. Thus, leakage current from transistors causes more severe problems in dynamic logic circuits than in static logic circuits. A logic circuit includes a first transistor whose off-state current is small and a second transistor whose gate is electrically connected to the first transistor. Electric charge is supplied to a node of the gate of the second transistor through the first transistor. Electric charge is supplied to the node through a first capacitor and a second capacitor. On/off of the second transistor is controlled depending on a state of the electric charge. The first transistor includes an oxide semiconductor in a channel formation region.

Claims

1. A semiconductor device comprising:

a first capacitor;

a second capacitor;

a first transistor; and

a second transistor,

wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other,

wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor,

wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor, and

wherein a channel formation region of the first transistor comprises an oxide semiconductor.

2. The semiconductor device according to claim 1, wherein the second transistor is an n-type channel transistor.

3. The semiconductor device according to claim 1, wherein the second transistor is a p-type channel transistor.

4. The semiconductor device according to claim 1,

wherein a node electrically connected to the gate electrode of the second transistor has electric charge,

wherein a first signal is input to the gate electrode of the second transistor through the first capacitor,

wherein a second signal is input to the gate electrode of the second transistor through the second capacitor, and

wherein the electric charge, the first signal and the second signal are configured to control a switching function of the second transistor.

5. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be dynamically reconfigured.

6. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises indium and zinc.

7. A semiconductor device comprising:

a first capacitor;

a second capacitor;

a first transistor;

a second transistor;

a third transistor;

a fourth transistor; and

an inverter,

wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other,

wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor,

wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, and

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor and the inverter.

8. The semiconductor device according to claim 7, wherein the first transistor comprises an oxide semiconductor.

9. The semiconductor device according to claim 7, wherein at least one of the third transistor and the fourth transistor comprises an oxide semiconductor.

10. The semiconductor device according to claim 7, wherein the second transistor is an n-type channel transistor.

11. The semiconductor device according to claim 7, wherein the second transistor is a p-type channel transistor.

12. The semiconductor device according to claim 7,

wherein a node electrically connected to the gate electrode of the second transistor has electric charge,

wherein a first signal is input to the gate electrode of the second transistor through the first capacitor,

wherein a second signal is input to the gate electrode of the second transistor through the second capacitor, and

wherein the electric charge, the first signal and the second signal are configured to control a switching function of the second transistor.

13. The semiconductor device according to claim 12,

wherein a logical operation is output from the inverter,

wherein the logical operation is a logical conjunction when the electric charge is in a first condition, and

wherein the logical operation is a logical disjunction when the electric charge is in a second condition.

14. The semiconductor device according to claim 13,

wherein the first signal and the second signal are high potentials in the first condition, and

wherein the first signal and the second signal are low potentials in the second condition.

15. The semiconductor device according to claim 7,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a high potential power source, and

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a low potential power source.

16. The semiconductor device according to claim 7, wherein the semiconductor device is configured to be dynamically reconfigured.

17. A method for driving a semiconductor device, the semiconductor device comprising a first capacitor, a second capacitor, a first transistor;

and a second transistor,

wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other,

wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor, and

wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,

the method comprising the steps of;

turning on the first transistor;

turning off the first transistor to hold electric charge of a node electrically connected to the gate electrode of the second transistor;

supplying a first signal to the gate electrode of the second transistor through the first capacitor;

supplying a second signal to the gate electrode of the second transistor through the second capacitor; and

controlling a switching function of the second transistor by the electric charge, the first signal and the second signal.

18. The method for driving a semiconductor device according to claim 17, wherein the first transistor comprises an oxide semiconductor.

19. The method for driving a semiconductor device according to claim 17, wherein the second transistor is an n-type channel transistor.

20. The method for driving a semiconductor device according to claim 17, wherein the second transistor is a p-type channel transistor.

21. The method for driving a semiconductor device according to claim 17, wherein the semiconductor device is configured to be dynamically reconfigured.

22. A method for driving a semiconductor device, the semiconductor device comprising a first capacitor, a second capacitor, a first transistor;

a second transistor, a third transistor, a fourth transistor and an inverter,

wherein one electrode of the first capacitor and one electrode of the second capacitor are electrically connected to each other,

wherein the one electrode of the first capacitor is electrically connected to a gate electrode of the second transistor,

wherein the one electrode of the second capacitor is electrically connected to one of a source electrode and a drain electrode of the first transistor,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to one of a source electrode and a drain electrode of the third transistor, and

wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor and the inverter,

the method comprising the steps of;

turning on the first transistor;

turning off the first transistor to hold electric charge of a node electrically connected to the gate electrode of the second transistor;

supplying a first signal to the gate electrode of the second transistor through the first capacitor;

supplying a second signal to the gate electrode of the second transistor through the second capacitor;

controlling a switching function of the second transistor by the electric charge, the first signal and the second signal; and

outputting a logical operation from the inverter.

23. The method for driving a semiconductor device according to claim 22, wherein the first transistor comprises an oxide semiconductor.

24. The method for driving a semiconductor device according to claim 22, wherein at least one of the third transistor and the fourth transistor comprises an oxide semiconductor.

25. The method for driving a semiconductor device according to claim 22, wherein the second transistor is an n-type channel transistor.

26. The method for driving a semiconductor device according to claim 22, wherein the second transistor is a p-type channel transistor.

27. The method for driving a semiconductor device according to claim 22, wherein the semiconductor device is configured to be dynamically reconfigured.

28. The method for driving a semiconductor device according to claim 22,

wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a high potential power source, and

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a low potential power source.

29. The method for driving a semiconductor device according to claim 22,

wherein the logical operation is a logical conjunction when the electric charge is in a first condition, and

wherein the logical operation is a logical disjunction when the electric charge is in a second condition.

30. The method for driving a semiconductor device according to claim 29,

wherein the first signal and the second signal are high potentials in the first condition, and

wherein the first signal and the second signal are low potentials in the second condition.