MRAM-based memory device with rotated gate

• US 8,542,525 B2
• Filed: 03/02/2011
• Issued: 09/24/2013
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Allegro Microsystems Incorporated (Sanken Electric Company Limited)
• Original Assignee: Crocus Technology S.A.
• Inventors: Berger, Neal, El Baraji, Mourad
• Primary Examiner(s): NGUYEN, DANG T
• Application Number:
  US13/038,473
• Publication Number:
  US 20110216580A1
• Time in Patent Office: 937 Days
• Field of Search: 365/158, 365/161, 365/171, 365/173, 365/189.01, 365/189.04, 365/189.07, 365/209, 365/185.29, 365/185.18, 365/185.05, 365/185.11
• US Class Current: 365/158
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

A memory device comprising: a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor; a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor; a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor; wherein the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and wherein each source line connecting the MRAM cells via the other end of the magnetic tunnel junction.

Claims

1. A memory device comprising:

a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor;

a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor;

a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor;

wherein

the memory device further comprises a plurality of source lines, each source line connecting MRAM cells along a row; and

wherein

each source line connecting the MRAM cells via the other end of the magnetic tunnel junction, wherein

either a word write bias voltage and a source write bias voltage, is applied respectively to the word line and source line connected to a selected MRAM cell, and the bit line connected to the selected MRAM cells is grounded, and a bit bias voltage is applied to bit lines connected to other MRAM cells in the same row as the selected MRAM cell, the bit bias voltage having a value corresponding substantially to the word write bias voltage, and the word lines connected to remaining MRAM cells are grounded, or

a word read bias voltage is applied via the word line to the gate of the select transistor connected to the selected MRAM cell, and a bit read bias voltage and a source read bias voltage is applied to the bit line and source line connected to the selected MRAM cell, and a bit bias voltage having a value corresponding to the source read bias voltage is applied to bit lines connected to other MRAM cells in the same row as the selected MRAM cell, and the word lines connected to remaining MRAM are grounded.

2. The memory device according to claim 1, wherein the select transistor is a high-power, low threshold voltage transistor.

3. The memory device according to claim 1, wherein the magnetic tunnel junction of each MRAM cell further comprises a reference layer having a fixed magnetization, a storage layer having a second magnetization switchable from a first stable direction to a second stable direction, and an insulating layer between the storage layer and the sense layer.

4. The memory device according to claim 3, wherein the magnetic tunnel junction further comprises a first antiferromagnetic layer pinning the magnetization of the reference layer and a second antiferromagnetic layer pinning the storage layer when the magnetic tunnel junction is at a temperature that is below a high threshold temperature.

5. Method of writing a memory device comprising:

a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor;

a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor;

a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor;

a plurality of source lines, each source line connecting MRAM cells along a row via the other end of the magnetic tunnel junction;

the method comprising;

selectively writing one of the thermally assisted switching magnetic random access memory cells by applying a word write bias voltage and a source write bias voltage, respectively to the word line and source line connected to the selected thermally assisted switching magnetic random access memory cells, and grounding the bit line connected to the selected thermally assisted switching magnetic random access memory cells; and

unselecting thermally assisted switching magnetic random access memory cells being in the same row as the thermally assisted switching magnetic random access memory cell being selectively written by applying via the corresponding bit line a bit bias voltage having a value corresponding substantially to the word write bias voltage, and unselecting other thermally assisted switching magnetic random access memory cells by grounding the corresponding word lines.

6. The method according to claim 5, wherein the source write bias voltage of the source line connected to the selected thermally assisted switching magnetic random access memory cells has a value that is higher than the word write bias voltage of the word line connected to the selected thermally assisted switching magnetic random access memory cells such as to pass a heating current through the magnetic tunnel junction of the MRAM cell being selectively written.

7. The method according to claim 6, wherein the source write bias voltage has a value corresponding to V_DD plus the write bias junction voltage across the magnetic tunnel junction when passing the heating current.

8. The method according to claim 6, wherein the magnitude of the heating current corresponds substantially to the magnitude of the saturation drain current of the select transistor.

9. The method according to claims from 6, wherein the magnetic tunnel junction of each MRAM cell comprises a reference layer having a fixed magnetization, a storage layer having a second magnetization switchable from a first stable direction to a second stable direction, and an insulating layer between the storage layer and the sense layer;

and wherein prior unselecting thermally assisted switching magnetic random access memory cells, the method further comprises switching the magnetization of the storage layer.

10. The method according to claim 9, wherein said switching the magnetization of the storage layer comprises a magnetic field generated by passing a field current in the bit line addressing said one of the thermally assisted switching magnetic random access memory cells.

11. The method according to claim 9, wherein said switching the magnetization of the storage layer comprises passing a spin-polarized current through the magnetic tunnel junction of said one of the thermally assisted switching magnetic random access memory cells, via the bit line addressing said one of the thermally assisted switching magnetic random access memory cells.

12. Method of reading a memory device comprising:

a plurality of magnetoresistive random access memory (MRAM) cells arranged in rows and columns, each MRAM cell comprising a magnetic tunnel junction and a select transistor, one end of the magnetic tunnel junction being electrically coupled to the source of the select transistor;

a plurality of word lines, each word line connecting MRAM cells along a row via the gate of their select transistor;

a plurality of bit lines, each bit line connecting MRAM cells along a column, each bit line connecting the MRAM cells via the drain of their select transistor;

a plurality of source lines, each source line connecting MRAM cells along a row via the other end of the magnetic tunnel junction;

the method comprising;

selectively reading one of the thermally assisted switching magnetic random access memory cells by applying a word read bias voltage via the word line to the gate of the select transistor connected to the selected thermally assisted switching magnetic random access memory cells, and applying a bit read bias voltage and a source read bias voltage to the bit line and source line addressing the selected thermally assisted switching magnetic random access memory cell; and

unselecting thermally assisted switching magnetic random access memory cells being in the same row as the thermally assisted switching magnetic random access memory cell being selectively read by applying, via the corresponding bit lines, a bit bias voltage having a value corresponding to the source read bias voltage, and unselecting other thermally assisted switching magnetic random access memory cells by grounding the corresponding word lines.

13. The method according to claim from 12, wherein the word read bias voltage of the word line connected to the selected thermally assisted switching magnetic random access memory cells is higher than the source read bias voltage, such as to generate a sense voltage and pass a sense current through the magnetic tunnel junction of the selected thermally assisted switching magnetic random access memory cell.

14. The method according to claim 13, wherein the word read bias voltage is such that the select transistor is operated in its linear region.

15. The method according to claim 13, wherein the sense voltage is 300 mV.