Semiconductor device and method for driving semiconductor device

• US 8,542,528 B2
• Filed: 08/03/2011
• Issued: 09/24/2013
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Sekine, Yusuke
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US13/197,438
• Publication Number:
  US 20120033505A1
• Time in Patent Office: 783 Days
• Field of Search: 365/185.03, 365/185.18, 365/185.22, 365/185.23, 365/185.24, 365/185.27, 365/185.29, 365/185.33
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/5685 using storage elements comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413

Abstract

A semiconductor device with a novel structure is provided, in which the operation voltage is reduced or the storage capacity is increased by reducing variation in the threshold voltages of memory cells after writing. The semiconductor device includes a plurality of memory cells each including a transistor including an oxide semiconductor and a transistor including a material other than an oxide semiconductor, a driver circuit that drives the plurality of memory cells, and a potential generating circuit that generates a plurality of potentials supplied to the driver circuit. The driver circuit includes a data buffer, a writing circuit that writes one potential of the plurality of potentials into each of the plurality of memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with data held in the data buffer or not.

Claims

1. A semiconductor device comprising:

a memory cell comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor;

a driver circuit configured to drive the memory cell; and

a potential generating circuit configured to generate potentials supplied to the driver circuit,

wherein the driver circuit comprises;

a data buffer configured to hold a first data to be written into the memory cell;

a writing circuit configured to write a second data with one potential of the potentials into the memory cell in accordance with the first data;

a reading circuit configured to read the second data written into the memory cell; and

a verifying circuit configured to verify whether the second data agrees with the first data or not,

wherein the one potential is a write potential for the memory cell where the second data agrees with the first data, and

wherein the write potential is changed to another potential of the potentials, for the memory cell where the second data does not agree with the first data.

2. The semiconductor device according to claim 1, wherein levels of the potentials are different from each other.

3. The semiconductor device according to claim 1, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

4. The semiconductor device according to claim 1,

wherein the writing circuit is electrically connected to one of a source and a drain of the first transistor, and

wherein the reading circuit is electrically connected to one of a source and a drain of the second transistor.

5. The semiconductor device according to claim 1, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

6. The semiconductor device according to claim 5, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

7. The semiconductor device according to claim 1, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

8. A semiconductor device comprising:

memory cells each comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor;

a driver circuit configured to drive the memory cells; and

a potential generating circuit configured to generate potentials supplied to the driver circuit,

wherein the driver circuit comprises;

a data buffer configured to hold a first data to be written into the memory cells;

a writing circuit configured to write a second data with one potential of the potentials into the memory cells in accordance with the first data;

a reading circuit configured to read the second data written into the memory cells; and

a verifying circuit configured to verify whether the second data agrees with the first data or not,

wherein the one potential is a write potential for a part of the memory cells where the second data agree with the first data; and

wherein the write potential is changed to another potential of the potentials, for the others of the memory cells where the second data does not agree with the first data.

9. The semiconductor device according to claim 8, wherein levels of the potentials are different from each other.

10. The semiconductor device according to claim 8, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

11. The semiconductor device according to claim 8,

wherein the writing circuit is electrically connected to one of a source and a drain of the first transistor, and

wherein the reading circuit is electrically connected to one of a source and a drain of the second transistor.

12. The semiconductor device according to claim 8, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

13. The semiconductor device according to claim 12, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 8, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

15. A method for driving a semiconductor device comprising a memory cell comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor, the method comprising the steps of:

holding a first data to be written into the memory cell in a data buffer;

writing a second data with one potential of potentials into the memory cell in accordance with the first data;

reading the second data written into the memory cell;

verifying whether the second data agrees with the first data or not; and

determining the one potential as a first write potential for the memory cell where the second data agrees with the first data, or changing the first write potential to another potential of the potentials, for the memory cell where the second data does not agree with the first data.

16. The method for driving the semiconductor device according to claim 15, further comprising the steps of:

writing the second data with the another potential into the memory cell after changing the first write potential to the another potential;

reading the second data written into the memory cell;

verifying whether the second data agrees with the first data or not; and

determining the another potential as a second write potential for the memory cell where the second data agrees with the first data, or changing the second write potential to still another potential of the potentials, for the memory cell where the second data does not agree with the first data.

17. The method for driving the semiconductor device according to claim 15, wherein levels of the potential are different from each other.

18. The method for driving the semiconductor device according to claim 15, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

19. The method for driving the semiconductor device according to claim 15, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

20. The method for driving the semiconductor device according to claim 19, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

21. The method for driving the semiconductor device according to claim 15, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.

22. A method for driving a semiconductor device comprising memory cells each comprising a first transistor including an oxide semiconductor and a second transistor including a material other than the oxide semiconductor, the method comprising the steps of:

holding a first data to be written into the memory cells in a data buffer;

writing a second data with one potential of potentials into the memory cells in accordance with the first data;

reading the second data written into the memory cells;

verifying whether the second data agrees with the first data or not;

determining the one potential as a first write potential for a first part of the memory cells where the second data agrees with the first data; and

changing the first write potential to another potential of the potentials, for a second part of the memory cells where the second data does not agree with the first data.

23. The method for driving the semiconductor device according to claim 22, further comprising the steps of:

writing the second data with the another potential into the second part of the memory cells after changing the first write potential to the another potential;

reading the second data written into the second part of the memory cells,

verifying whether the second data agrees with the first data or not;

determining the another potential as a second write potential for the second part of the memory cells where the second data agree with the first data after verifying; and

changing the second write potential to still another potential of the potentials, for a third part of the memory cells where the second data does not agree with the first data.

24. The method for driving the semiconductor device according to claim 22, wherein levels of the potentials are different from each other.

25. The method for driving the semiconductor device according to claim 22, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor.

26. The method for driving the semiconductor device according to claim 22, wherein the second transistor comprises a channel formation region provided in a substrate including a semiconductor material.

27. The method for driving the semiconductor device according to claim 26, wherein the substrate is a single crystal semiconductor substrate or an SOI substrate.

28. The method for driving the semiconductor device according to claim 22, wherein the oxide semiconductor comprises an oxide semiconductor material including In, Ga, and Zn.