Specialized processing block for programmable integrated circuit device

• US 8,543,634 B1
• Filed: 03/30/2012
• Issued: 09/24/2013
• Est. Priority Date: 03/30/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Xu, Lei, Mauer, Volker, Perry, Steven
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US13/435,133
• Time in Patent Office: 543 Days
• Field of Search: 708/316, 708/523, 708/603, 326 37- 41, 326/47
• US Class Current: 708/603
• CPC Class Codes: G06F 2207/5523 Calculates a power, e.g. the square, of a number or a function, e.g. polynomials
• CPC Class Codes: G06F 7/552 Powers or roots , e.g. Pythagorean sums

Abstract

A specialized processing block such as a DSP block may be enhanced by including direct connections that allow the block output to be directly connected to either the multiplier inputs or the adder inputs of another such block. A programmable integrated circuit device may includes a plurality of such specialized processing blocks. The specialized processing block includes a multiplier having two multiplicand inputs and a product output, an adder having as one adder input the product output of the multiplier, and having a second adder input and an adder output, a direct-connect output of the adder output to a first other one of the specialized processing block, and a direct-connect input from a second other one of the specialized processing block. The direct-connect input connects a direct-connect output of that second other one of the specialized processing block to a first one of the multiplicand inputs.

Claims

1. A specialized processing block on a programmable integrated circuit device, said specialized processing block comprising:

a multiplier having two multiplicand inputs and a product output;

an adder having as one adder input said product output of said multiplier, and having a second adder input and an adder output;

a direct-connect output of said adder output to a first other said specialized processing block; and

a direct-connect input from a second other said specialized processing block, said direct-connect input connecting a direct-connect output of said adder output of said second other said specialized processing block to a first one of said multiplicand inputs.

2. The specialized processing block of claim 1 further comprising first multiplexer circuitry for selectably connecting said direct-connect input to said first one of said multiplicand inputs and said second adder input.

3. The specialized processing block of claim 2 further comprising:

at least one input register receiving a value input from outside said specialized processing block and providing said value to a second one of said multiplicand inputs;

an input register chain output directly connecting an output of said at least one input register to said first other said specialized processing block; and

an input register chain input directly connecting an input register chain output of said second other said specialized processing block to said second one of said multiplicand inputs.

4. The specialized processing block of claim 3 further comprising an input chain output multiplexer selectably connecting said second one of said multiplicand inputs and said output of said at least one input register to said input register chain output.

5. The specialized processing block of claim 4 wherein said input chain output multiplexer selectably connects said input register chain output to said output of said at least one input register and both said first and second ones of said multiplicand inputs.

6. The specialized processing block of claim 3 further comprising an input chain input multiplexer selectably connecting said output of said at least one input register and said input register chain input to said second one of said multiplicand inputs.

7. The specialized processing block of claim 1 further comprising at least one pipeline register on each of said multiplicand inputs, said one adder input and said second adder input.

8. A programmable integrated circuit device comprising:

programmable logic resources;

programmable interconnect resources for routing signals among said programmable logic resources; and

a plurality of specialized processing blocks, each of said specialized processing blocks comprising;

a multiplier having two multiplicand inputs and a product output;

an adder having as one adder input said product output of said multiplier, and having a second adder input and an adder output;

a direct-connect output of said adder output to a first other one of said specialized processing blocks; and

a direct-connect input from a second other one of said specialized processing blocks, said direct-connect input connecting a direct-connect output of said adder output of said second other one of said specialized processing blocks to a first one of said multiplicand inputs.

9. The programmable integrated circuit device of claim 8 wherein each of said specialized processing blocks further comprises first multiplexer circuitry for selectably connecting said direct-connect input to said first one of said multiplicand inputs and said second adder input.

10. The programmable integrated circuit device of claim 8 wherein each of said specialized processing blocks further comprises:

at least one input register receiving a value input from outside said specialized processing block and providing said value to a second one of said multiplicand inputs;

an input register chain output directly connecting an output of said at least one input register to said first other one of said specialized processing blocks; and

an input register chain input directly connecting an input register chain output of said second other one of said specialized processing blocks to said second one of said multiplicand inputs.

11. The programmable integrated circuit device of claim 10 wherein each of said specialized processing blocks further comprises an input chain output multiplexer selectably connecting said second one of said multiplicand inputs and said output of said at least one input register to said input register chain output.

12. The programmable integrated circuit device of claim 11 wherein said input chain output multiplexer selectably connects said input register chain output to said output of said at least one input register and both said first and second ones of said multiplicand inputs.

13. The programmable integrated circuit device of claim 10 further comprising an input chain input multiplexer selectably connecting said output of said at least one input register and said input register chain input to said second one of said multiplicand inputs.

14. The programmable integrated circuit device of claim 8 wherein each said specialized processing block further comprises at least one pipeline register on each of said multiplicand inputs, said one adder input and said second adder input.

15. A method of configuring a programmable integrated circuit device to calculate a polynomial having a number of terms, wherein said programmable integrated circuit device comprises:

programmable logic resources,

programmable interconnect resources for routing signals among said programmable logic resources, and

a plurality of specialized processing blocks, each of said specialized processing blocks comprising;

a multiplier having two multiplicand inputs and a product output,

an adder having as one adder input said product output of said multiplier, and having a second adder input and an adder output,

a direct-connect output of said adder output to a first other one of said specialized processing blocks, and

a direct-connect input from a second other one of said specialized processing blocks, said direct-connect input connecting a direct-connect output of said adder output of said second other one of said specialized processing blocks to first multiplexer circuitry for selectably connecting said direct-connect input to said first one of said multiplicand inputs and said second adder input;

said method comprising, for each respective specialized processing block among a plurality of said specialized processing blocks corresponding to said number of said terms;

configuring said first multiplexer circuitry to connect said direct-connect input to said first one of said multiplicand inputs.

16. The method of claim 15 wherein each of said specialized processing blocks further comprises:

at least one input register receiving a value input from outside said specialized processing block and providing said value to a second one of said multiplicand inputs,

an input register chain output including an input chain output multiplexer selectably directly connecting said second one of said multiplicand inputs and said output of said at least one input register to said first other one of said specialized processing blocks, and

an input register chain input including an input chain input multiplexer selectably directly connecting said output of said at least one input register and said input register chain output of said second other one of said specialized processing blocks to said second one of said multiplicand inputs;

said method further comprising, for at least one of said specialized processing blocks;

configuring said input chain output multiplexer to connect said second one of said multiplicand inputs to said input register chain output.

17. The method of claim 16 wherein said input chain output multiplexer selectably connects said input register chain output to said output of said at least one input register and both said first and second ones of said multiplicand inputs;

said method further comprising, for at least one of said specialized processing blocks;

configuring said input chain output multiplexer to connect said first one of said multiplicand inputs to said input register chain output for sharing said first one of said multiplicand inputs with another one of said specialized processing blocks.

18. The method of claim 17 further comprising configuring, in said another one of said specialized processing blocks, said input chain input multiplexer to connect said output of said at least one input register to said second one of said multiplicand inputs.

19. The method of claim 15 further comprising configuring pipeline registers on said multiplicand inputs, said one adder input and said second adder input.