Flash-memory device with RAID-type controller
First Claim
1. A smart flash drive comprising:
- a top-level smart storage switch that is connected upstream to a host and has a plurality of downstream interfaces;
a plurality of second-level smart storage switches each having an upstream interface to the top-level smart storage switch and a plurality of downstream interfaces;
an operation unit, in a data path of the top-level smart storage switch, for performing an operation upon data to be stored in a physical block of flash memory, wherein the operation is a compression or an encryption;
a plurality of single-chip flash devices (SCFD'"'"'s), a SCFD comprising;
a plurality of physical blocks of flash memory;
a low-level wear-level controller that performs wear-leveling swapping of physical blocks within that SCFD based on a wear-level count (WLC) for each physical block;
a low-level mapper that maps a low-level logical address to a physical-block address (PBA) for physical blocks within the SCFD;
a top-level Redundant Array of Individual Disks (RAID) controller, in the top-level smart storage switch, the top-level RAID controller striping host data into a plurality of top-level stripes to the plurality of second-level smart storage switchesa plurality of second-level RAID controllers in the plurality of second-level smart storage switches, wherein a second-level RAID controller stripes data received on the upstream interface of a second-level smart storage switch into a plurality of second-level stripes to the plurality of SCFD connected to the second-level smart storage switch; and
an interleaving controller, in the SCFD, for interleaving data received by the SCFD across multiple planes of flash memory.
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Accused Products
Abstract
A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD'"'"'s). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.
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Citations
18 Claims
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1. A smart flash drive comprising:
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a top-level smart storage switch that is connected upstream to a host and has a plurality of downstream interfaces; a plurality of second-level smart storage switches each having an upstream interface to the top-level smart storage switch and a plurality of downstream interfaces; an operation unit, in a data path of the top-level smart storage switch, for performing an operation upon data to be stored in a physical block of flash memory, wherein the operation is a compression or an encryption; a plurality of single-chip flash devices (SCFD'"'"'s), a SCFD comprising; a plurality of physical blocks of flash memory; a low-level wear-level controller that performs wear-leveling swapping of physical blocks within that SCFD based on a wear-level count (WLC) for each physical block; a low-level mapper that maps a low-level logical address to a physical-block address (PBA) for physical blocks within the SCFD; a top-level Redundant Array of Individual Disks (RAID) controller, in the top-level smart storage switch, the top-level RAID controller striping host data into a plurality of top-level stripes to the plurality of second-level smart storage switches a plurality of second-level RAID controllers in the plurality of second-level smart storage switches, wherein a second-level RAID controller stripes data received on the upstream interface of a second-level smart storage switch into a plurality of second-level stripes to the plurality of SCFD connected to the second-level smart storage switch; and an interleaving controller, in the SCFD, for interleaving data received by the SCFD across multiple planes of flash memory. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A smart flash device comprising:
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a plurality of single-chip flash devices (SCFD'"'"'s), a SCFD comprising; a plurality of physical blocks of flash memory; a low-level wear-level controller that performs wear-leveling swapping of physical blocks within that SCFD based on a wear-level count (WLC) for the physical block; a low-level mapper that maps a low-level logical address to a physical-block address (PBA) for physical blocks within the SCFD; a bad-block manager that disables and counts bad blocks within the SCFD to generate a bad-block number (BBN) for the SCFD; wherein the SCFD generates a maximum WLC from the WLC for physical blocks in the SCFD and reports over an upstream interface the maximum WLC and the BBN; a low-level smart storage switch that comprises; a plurality of SCFD drivers, a SCFD driver for connecting to a SCFD in the plurality of SCFD; an upstream interface that receives data from an upstream device; a controller that stripes the data from the upstream device among the plurality of SCFD, wherein a stripe size is equal to a channel size of the SCFD; a structure register that stores the maximum WLC and the BBN for the plurality of SCFD connected to the low-level smart storage switch; a mid-level wear leveler, reading the maximum WLC and BBN from the structure register, having a comparator that compares the maximum WLC to a WLC threshold and activates a wear-leveling swap when one of the maximum WLC stored in the structure register exceeds the WLC threshold; and a direct-memory access (DMA) engine that is programmed to swap data from a source physical block in a target SCFD that has a BBN that is a largest BBN stored in the structure register, the DMA engine swapping data to a target physical block in a source SCFD that has a maximum WLC that is lower than other maximum WLC stored in the structure register, whereby physical blocks of flash memory in the SCFD are wear-leveled by the low-level smart storage switch that examines maximum WLC and BBN stored in the structure register. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A multi-level flash device comprising:
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a top-level smart storage switch comprising a smart storage switch connected upstream to a host and downstream to a plurality of second-level smart storage switches; wherein a second-level smart storage switch in the plurality of second-level smart storage switches comprises a smart storage switch connected downstream to a plurality of endpoint devices and upstream to the top-level smart storage switch; wherein an endpoint device comprises a single-chip flash device (SCFD) having physical blocks of flash memory; wherein the smart storage switch comprises; downstream means for connecting to a plurality of downstream devices; upstream means for connecting to an upstream device; controller means for dividing upstream data into a plurality of stripes, each stripe being sent to a different downstream device; structure register means for storing wear-level counts and bad-block counts received from downstream devices; upstream reporting means for reporting a maximum of the wear-level counts to the upstream device and for reporting a maximum of the bad-block counts to the upstream device; wear leveling means for swapping physical blocks of two downstream devices selected using the wear-level counts and bad-block counts stored in the structure register means, encryptor/decryptor means, in a data path of the top-level smart storage switch, for encrypting data to be stored in a block in the physical blocks of flash memory, and for decrypting data read from a block in the physical blocks of flash memory, whereby wear leveling is performed on multiple levels. - View Dependent Claims (16, 17, 18)
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Specification