Invalidating translation lookaside buffer entries in a virtual machine (VM) system

• US 8,543,772 B2
• Filed: 12/02/2010
• Issued: 09/24/2013
• Est. Priority Date: 09/30/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cota-Robles, Eric C., Glew, Andy, Jeyasingh, Stalinselvaraj, Kagi, Alain, Kozuch, Michael A., Neiger, Gilbert, Uhlig, Richard
• Primary Examiner(s): CHOE, YONG J
• Application Number:
  US12/959,109
• Publication Number:
  US 20120117300A1
• Time in Patent Office: 1,027 Days
• Field of Search: 711/133, 711/145, 711/6, 711/E12.016
• US Class Current: 711/145
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1036 for multiple virtual address spaces, e.g. segmentation G06F12/1045 takes precedence
• CPC Class Codes: G06F 2212/151 Emulated environment, e.g. virtual machine
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP

Abstract

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.

Claims

1. An apparatus comprising:

a hardware managed stack to hold a plurality of virtual machine extension (VMX) mask word values corresponding to a plurality of virtual machines (VMs), wherein a current VMX mask word value of the plurality of VMX mask word values, which corresponds to a current VM of the plurality of VMs, is to be utilized to mask access by the current VM to a VMX control word; and

a translation lookaside buffer (TLB) having a plurality of TLB entries, wherein a TLB entry of the plurality of TLB entries is to be associated with a virtual machine extension (VMX) tag word, and invalidation logic to determine the TLB entry is to be invalidated responsive to a comparison of the VMX tag word and the VMX control word indicating the TLB entry is to be invalidated in response to an invalidation operation being performed.

2. The apparatus of claim 1 wherein the invalidation operation is selected from a group consisting of (1) a load of a first control register conditioned on a global bit, (2) an execution of a page invalidate instruction, (3) task switch involving change of at least one virtual memory related control register, (4) a load of a second control register that modifies one of a protected mode indicator and a page mode indicator, and (5) a loading of a third control register that modifies one of page size extension (PSE), a page global enable (PGE), and a physical address extension (PAE).

3. The apparatus of claim 1 further comprising a first register to hold the VMX control word and a second register to hold the current VMX mask word value.

4. The apparatus of claim 1 further comprising a memory to hold a virtual machine control structure (VMCS), wherein the VMX control word is to be held in the VMCS.

5. The apparatus of claim 1 wherein the invalidation logic to determine the TLB entry is to be invalidated responsive to a comparison of the VMX tag word and the VMX control word indicating the TLB entry is to be invalidated in response to an invalidation operation being performed comprises:

determining the TLB entry is to be invalidated in response to the invalidation operation being performed and the VMX tag word matching the VMX control word.

6. The apparatus of claim 1 wherein the VMX control word is configurable a non-virtual machine execution mode.

7. The apparatus of claim 1 further comprising a second VMX control word, wherein the invalidation logic is to determine the TLB entry is to be invalidated responsive to a logical AND of the VMX tag word and the second VMX control word matches the VMX control word.

8. The apparatus of claim 7 wherein a logical AND of the current VMX mask word and a previous VMX mask word matches the previous VMX mask word.

9. The apparatus of claim 1 wherein the VMX tag word and the VMX control word are determined by execution of a specified processor instruction in a specified manner.

10. The apparatus of claim 1 wherein a size of a VMX tag word and the VMX control word is determined by executing a specified processor instruction in a specified manner.

11. The apparatus of claim 10 wherein the specified instruction is a central processor unit identification (CPUID) instruction and the specified manner is to have a specified value in a control when the CPUID instruction is executed.

12. A processor comprising:

a virtual machine extension (VMX) mask word to mask access to VMX control (TLBVMX) word during a VMX mode of operation;

a translation lookaside buffer (TLB) having a plurality of TLB entries, each TLB entry being associated with a virtual machine extension (VMX) tag word; and

invalidation logic, in response to an invalidation operation during the VMX mode of operation, to invalidate each TLB entry being associated with a VMX tag word that matches the TLBVMX word.

13. The processor of claim 12 wherein the invalidation operation is selected from a group consisting of (1) a loading of the first control register conditioned on a global bit, (2) an execution of a page invalidate instruction, (3) a task switch involving change of at least one virtual memory related control register, and (4) a loading of the third control register that modifies one of a page size extension (PSE), a page global enable (PGE), and a physical address extension (PAE).

14. The processor of claim 12 wherein invalidation logic, in response to an invalidation operation during the virtual machine mode of operation, to invalidate each TLB entry being associated with a VMX tag word that matches the TLBVMX word comprises:

the invalidation logic, in response to an invalidation operation during the virtual machine mode of operation, to updated each VMX tag word that matches the TLBVMX word to an invalid value to indicate each TLB entry being associated with each VMX tag word that matches the TLBVMX word is invalid.

15. The processor of claim 12 further comprising a hardware management stack to hold a plurality of mask values for the VMX mask word, wherein each of the plurality of mask values correspond to a layered virtual machine.

16. The processor of claim 12 wherein the invalidation logic, in response to an invalidation operation during a non-VMX mode of operation, to invalidate a TLB entry of the plurality of TLB entries irrespective of the VMX tag word being associated with the TLB entry.

17. An apparatus comprising:

execution resources to execute a first virtual machine (VM) during a virtual machine extensions (VMX) mode of execution;

a control field to hold a current VM value, the current VM value to include a first VM value during execution of the first VM;

a mask field to provide masked access for at least the first VM to the control field; and

a translation lookaside buffer (TLB) including a plurality of TLB entries, wherein a first TLB entry of the plurality of TLB entries is to be associated with a first virtual machine extension (VMX) tag field and a second TLB entry of the plurality of TLB entries is to be associated with a second VMX tag field, the first VMX tag field to hold a first value to indicate the first TLB entry is associated with the first VM and the second VMX tag field to hold a second value to indicate the second TLB entry is associated with a second VM, and wherein, in response to an invalidation operation, the first TLB entry is determined to be invalidated based on the first value held in the first VMX tag field and the current value held in the control field.

18. The apparatus of claim 17, wherein the execution resources are also to execute a virtual machine monitor (VMM) during non-VMX mode of execution.

19. The apparatus of claim 18, further comprising a hardware-managed stack, wherein in response to an entrance into the first VM, the VMM is to provide a Previously Added mask value to be held in the mask field and an old value held in the mask field is to be pushed on the hardware-managed stack.

20. The apparatus of claim 19, wherein the Previously Added mask value is logically ORed with the old mask value before the Previously Added mask value is held in the mask field.

21. The apparatus of claim 20, wherein the old mask value is popped off the hardware-managed stack and restored the mask field in response to exiting the first VM.

22. The apparatus of claim 18, wherein a system memory is coupled to the apparatus, the system memory to hold a virtual machine control structure (VMCS), the VMCS to hold a state of the VMM.

23. The apparatus of claim 22, wherein the VMCS is also to hold the control field and the mask field.

24. The apparatus of claim 18, wherein the control field and the mask field are included in control registers.

25. The apparatus of claim 17, wherein the invalidation operation is selected from a group consisting of a load a control register operation, an invalidate a page operation, and a task switch operation.

26. The apparatus of claim 17, wherein in response to an invalidation operation, the first TLB entry is determined to be invalidated based on the first value held in the first VMX tag field and the current value held in the control field comprises determining the first TLB entry is to be invalided in response to the first VMX tag field and the current value being the same.