Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs

• US 8,543,954 B1
• Filed: 09/02/2008
• Issued: 09/24/2013
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Keller, Igor, Kariat, Vinod, Tam, King Ho
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US12/203,115
• Time in Patent Office: 1,848 Days
• Field of Search: 716/106, 716/108, 716/111, 716/115, 716/124, 716/132, 716/134, 716/136, 703/2, 703/14, 703/15
• US Class Current: 716/115
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Systems, apparatus, and methods of static timing analysis for an integrated circuit design in the presence of noise are disclosed. The integrated circuit design undergoing analysis may be partitioned into a plurality of subcircuit stages. Each subcircuit stage in the integrated circuit design may be modeled to include a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network. Associated with each subcircuit stage is a set of related edges of a design graph to compute signal propagation delay. For each subcircuit stage, full timing delays of each edge can be concurrently computed. This includes concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

Claims

1. A method of static timing analysis for an integrated circuit design in the presence of noise, the method comprising:

partitioning an integrated circuit design into a plurality of subcircuit stages;

modeling each subcircuit stage of the integrated circuit design with a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network of at least one victim net and at least one aggressor net coupled together, wherein each subcircuit stage of the integrated circuit design includes a set of related edges of a design graph to compute signal propagation delay;

for each subcircuit stage, concurrently computing full timing delays for each edge of the design graph, including concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network; and

wherein one or more of the partitioning, the modeling, and the concurrent computing are automatically performed with a processor.

2. The method of claim 1, wherein

the base timing delays are computed for the nominal response to a victim transition of the at least one victim driver and the interconnect network for each edge without cross-talk noise from any aggressor driver.

3. The method of claim 2, wherein

the full timing delays are computed by

independently computing a glitch response of each circuit stage for each aggressor driver at an input to the at least one receiver in response to an aggressor transition of the respective aggressor driver;

optimizing alignment of the victim transition and the aggressor transitions in each stage to determine a worse case aggressor alignment for worst case delay change; and

combining all of the glitch responses together with the nominal response to determine the full timing delay of each subcircuit stage.

4. The method of claim 3, wherein

the combining of all of the glitch responses together with the nominal response is performed by using a perturbation method.

5. The method of claim 1, further comprising:

tabulating the nominal response, the glitch responses and the full timing delays of each circuit stage for use in static timing analysis of the integrated circuit design.

6. The method of claim 1, wherein

the at least one victim driver and the at least one aggressor driver are each modeled by a multi-CCC current source model.

7. The method of claim 1, wherein

the modeling of each subcircuit stage of the integrated circuit design includes

identifying the at least one victim driver, the at least one aggressor driver, and the at least one receiver coupled to the at least one victim net and the at least one aggressor net;

and

coupling parasitic resistances and capacitances to the at least one victim driver, the at least one aggressor driver, and the at least one receiver to model the at least one victim net and the at least one aggressor net.

8. The method of claim 7, wherein

the modeling of each subcircuit stage of the integrated circuit design further includes

determining an input capacitance of the at least one receiver to model the at least one receiver.

9. The method of claim 8, wherein

the modeling of each subcircuit stage of the integrated circuit design further includes

reading a cell library file to determine a gate model for each of the at least one victim driver and the at least one aggressor driver.

10. The method of claim 9, wherein

the gate model is a multi-CCC current source model.

11. A machine readable product for static timing analysis of an integrated circuit design, the machine readable product comprising:

a non-transitory machine readable medium having machine readable program code stored therein including

machine readable program code to automatically partition an integrated circuit design into a plurality of subcircuit stages;

machine readable program code to automatically model each subcircuit stage of the integrated circuit design with a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network of at least one victim net and at least one aggressor net coupled together, wherein each subcircuit stage of the integrated circuit design includes a set of related edges of a design graph to compute signal propagation delay; and

machine readable program code to automatically concurrently compute full timing delays for each edge of each subcircuit stage, including concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays for at least one glitch response to the at least one aggressor driver and the interconnect network.

12. The machine readable product of claim 11, wherein

the base timing delays are automatically computed by the machine readable program code for the nominal response to a victim transition of the at least one victim driver and the interconnect network for each edge without cross-talk noise from any aggressor driver.

13. The machine readable product of claim 11, wherein

the machine readable program code to automatically concurrently compute the full timing delays includes

machine readable program code to automatically independently compute a glitch response of each circuit stage for each aggressor driver at an input to the at least one receiver in response to an aggressor transition of the respective aggressor driver;

machine readable program code to automatically optimize alignment of the victim transition and the aggressor transitions in each stage to determine a worse case aggressor alignment for worst case delay change; and

machine readable program code to automatically combine all of the glitch responses together with the normal response to determine the full timing delay of each subcircuit stage.

14. The machine readable product of claim 13, wherein

the machine readable program code to automatically combine all of the glitch responses together with the normal response uses a perturbation method.

15. The machine readable product of claim 11, wherein

the machine readable program code to automatically concurrently compute model each subcircuit stage of the integrated circuit design includes

machine readable program code to automatically identify the at least one victim driver, the at least one aggressor driver, and the at least one receiver coupled to the at least one victim net and the at least one aggressor net;

and

machine readable program code to automatically couple parasitic resistances and capacitances to the at least one victim driver, the at least one aggressor driver, and the at least one receiver to model the at least one victim net and the at least one aggressor net.

16. The machine readable product of claim 15, wherein

the machine readable program code to automatically concurrently compute model each subcircuit stage of the integrated circuit design further includes

machine readable program code to automatically determine an input capacitance of the at least one receiver to model the at least one receiver.

17. The machine readable product of claim 16, wherein

the machine readable program code to automatically concurrently compute model each subcircuit stage of the integrated circuit design includes

machine readable program code to automatically read a cell library file to determine a gate model for each of the at least one victim driver and the at least one aggressor driver.

18. The machine readable product of claim 17, wherein

the gate model is a multi-CCC current source model.

19. A system for static timing analysis of an integrated circuit design, the system comprising:

a processor to execute instructions to perform operations in analyzing timing of an integrated circuit design; and

a storage device coupled to the processor, the storage device to store instructions that when executed by the processor cause the processor to perform operations including

partitioning an integrated circuit design into a plurality of subcircuit stages;

modeling each subcircuit stage of the integrated circuit design with a model of at least one victim driver, at least one aggressor driver, at least one receiver, and an interconnect network of at least one victim net and at least one aggressor net coupled together, wherein each subcircuit stage of the integrated circuit design includes a set of related edges of a design graph to compute signal propagation delay; and

for each subcircuit stage, concurrently computing full timing delays for each edge of the design graph, including concurrently computing base timing delays for a nominal response to the at least one victim driver and the interconnect network and noise related timing delays in response to the at least one aggressor driver and the interconnect network.

20. The system of claim 19, wherein

the base timing delays are computed for the nominal response to a victim transition of the at least one victim driver and the interconnect network for each edge without cross-talk noise from any aggressor driver.

21. The system of claim 20, wherein

the full timing delays are computed by

independently computing a glitch response of each circuit stage for each aggressor driver at an input to the at least one receiver in response to an aggressor transition of the respective aggressor driver;

optimizing alignment of the victim transition and the aggressor transitions in each stage to determine a worse case aggressor alignment for worst case delay change; and

combining all of the glitch responses together with the nominal response to determine the full timing delay of each subcircuit stage.

22. The system of claim 21, wherein

the combining of all of the glitch responses together with the nominal response is performed by using a perturbation method.

23. The system of claim 19, further comprising:

tabulating the nominal response, the glitch responses and the full timing delays of each circuit stage for use in static timing analysis of the integrated circuit design.

24. The system of claim 19, wherein

the at least one victim driver and the at least one aggressor driver are each modeled by a multi-CCC current source model.

25. The system of claim 19, wherein

the modeling of each subcircuit stage of the integrated circuit design includes

identifying the at least one victim driver, the at least one aggressor driver, and the at least one receiver coupled to the at least one victim net and the at least one aggressor net;

and

coupling parasitic resistances and capacitances to the at least one victim driver, the at least one aggressor driver, and the at least one receiver to model the at least one victim net and the at least one aggressor net.

26. The system of claim 25, wherein

the modeling of each subcircuit stage of the integrated circuit design further includes

determining an input capacitance of the at least one receiver to model the at least one receiver.

27. The system of claim 26, wherein

the modeling of each subcircuit stage of the integrated circuit design further includes

reading a cell library file to determine a gate model for each of the at least one victim driver and the at least one aggressor driver.

28. The system of claim 27, wherein

the gate model is a multi-CCC current source model.