Implementing storage adapter performance optimization with chained hardware operations minimizing hardware/firmware interactions

• US 8,544,029 B2
• Filed: 05/24/2011
• Issued: 09/24/2013
• Est. Priority Date: 05/24/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bakke, Brian E., Bowles, Brian L., Carnevale, Michael J., Galbraith, Robert E. II, Gerhard, Adrian C., Iyer, Murali N., Moertl, Daniel F., Moran, Mark J., Radhakrishnan, Gowrisankar, Weckwerth, Rick A., Ziebarth, Donald J.
• Primary Examiner(s): Ho, Andy
• Assistant Examiner(s): SEYE, ABDOU K
• Application Number:
  US13/114,107
• Publication Number:
  US 20120304198A1
• Time in Patent Office: 854 Days
• Field of Search: None
• US Class Current: 719/318
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A method and controller for implementing storage adapter performance optimization with chained hardware operations minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and one or more processors. An event queue is coupled to at least one processor notifying the processor of a plurality of predefined events. A control block is designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry. A plurality of the control blocks are selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.

Claims

1. A data storage system comprising:

a controller comprising

a plurality of hardware engines;

a processor;

an event queue coupled to the processor notifying the processor of a plurality of predefined events;

a control block of a plurality of control blocks designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry;

the hardware engine performing a plurality of storage input output adapter (IOA) operations responsive to said control blocks, said operations including buffer allocate;

update parity footprint, read of data, write of data, and buffer deallocate, and

said plurality of the control blocks selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.

2. The data storage system as recited in claim 1 wherein said predefined chain includes sequential control blocks stored within contiguous memory.

3. The data storage system as recited in claim 1 wherein each said control block of said plurality of control blocks is selectively linked to any other control block.

4. The data storage system as recited in claim 1 wherein said control block is selectively linked to a plurality of other control blocks to provide parallel dispatch of controls applied to respective hardware engines.

5. The data storage system as recited in claim 1 wherein said predefined chain defines controls applied to respective hardware engines.

6. The data storage system as recited in claim 1 wherein each said control block includes a control block common header including a control block identification (ID), a control block chain position, and a next control block ID.

7. The data storage system as recited in claim 6 wherein said control block ID identifies one of the plurality of hardware engines, and said next control block ID identifies one of the plurality of hardware engines.

8. The data storage system as recited in claim 6 wherein said control block chain position identifies a first in chain, a last in chain, middle in linked chain, or stand alone control block.

9. The data storage system as recited in claim 6 wherein said control block common header includes a predefined hardware event queue entry selectively written when the control block completes.

10. The data storage system as recited claim 6 wherein said control block common header includes a predefined hardware event queue entry, said predefined hardware event queue entry is written when a stand alone control block completes and when a last in chain control block completes.

11. The data storage system as recited in claim 1 wherein a predefined hardware event queue entry is written when one said control block of said plurality of control blocks fails with an error.

12. The data storage system as recited in claim 1 wherein said predefined chain of the plurality of the control blocks is executed by respective hardware engines without any processor interaction.

13. A method for implementing storage adapter performance optimization in a data storage system comprising:

using the data storage system to perform the steps of;

providing a controller comprising a plurality of hardware engines; and

a processor;

providing an event queue coupled to the processor notifying the processor of a plurality of predefined events;

providing a control block of a plurality of control blocks designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry;

performing a plurality of storage input output adapter (IOA) operations with the hardware engine responsive to said control blocks, said operations including buffer allocate;

update parity footprint, read of data, write of data, and buffer deallocate and providing said plurality of the control blocks selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor.

14. The method as recited in claim 13 wherein providing a control block includes providing a control block common header including a control block identification (ID), a control block chain position, and a next control block ID.

15. The method as recited in claim 13 wherein providing an event queue includes writing an event queue entry responsive to completion of a stand alone control block and responsive to completion of a last in chain control block.

16. The method as recited in claim 13 wherein providing an event queue includes writing an event queue entry responsive to one said control block of said plurality of control blocks fail with an error.

17. The method as recited in claim 13 wherein providing a plurality of the control blocks selectively arranged in a predefined chain includes storing sequential control blocks within a dynamic random access memory (DRAM).

18. The method as recited in claim 13 includes respective hardware engines executing the plurality of the control blocks in said predefined chain without any processor interaction.

19. A controller for implementing storage adapter performance optimization in a data storage system comprising:

a processor;

a plurality of hardware engines;

an event queue coupled to the processor notifying the processor of a plurality of predefined events;

a control block of a plurality of control blocks designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry;

the hardware engine performing a plurality of storage input output adapter (IOA) operations responsive to said control blocks, said operations including buffer allocate;

update parity footprint, read of data, write of data, and buffer deallocate, and

said plurality of the control blocks selectively arranged in a predefined chain;

said predefined chain being executed by respective hardware engines without any processor interaction.

20. The controller as recited in claim 19 wherein each said control block includes a common header including a control block identification (ID), a control block chain position, and a next control block ID.

21. The controller as recited in claim 19 wherein said predefined chain includes sequential control blocks stored within contiguous memory.

22. A design structure embodied in a non-transitory machine readable medium used in a design process, the design structure used in the manufacture of a semiconductor chip, the design structure comprising:

a controller circuit tangibly embodied in the non-transitory machine readable medium used in the design process, said controller circuit for implementing storage adapter performance optimization in a data storage system, said controller circuit comprising;

a plurality of hardware engines;

a processor;

an event queue coupled to the processor notifying the processor of a plurality of predefined events;

a control block of a plurality of control blocks designed to control an operation in one of the plurality of hardware engines including the hardware engine writing an event queue entry;

the hardware engine performing a plurality of storage input output adapter (IOA) operations responsive to said control blocks, said operations including buffer allocate;

update parity footprint, read of data, write of data, and buffer deallocate, and

said plurality of the control blocks selectively arranged in a predefined chain to minimize the hardware engine writing event queue entries to the processor, wherein the design structure, when read and used in the manufacture of the semiconductor chip produces a chip comprising said controller circuit.

23. The design structure of claim 22, wherein the design structure comprises a netlist, which describes said controller circuit.

24. The design structure of claim 22, wherein the design structure resides on the non-transitory machine readable medium as a data format used for the exchange of layout data of integrated circuits.

25. The design structure of claim 22, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.