Method of manufacturing display device including thin film transistor

• US 8,546,164 B2
• Filed: 11/10/2011
• Issued: 10/01/2013
• Est. Priority Date: 04/03/2008
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Jeong, Jae-Kyeong, Mo, Yeon-Gon, Yang, Hui-Won, Jeong, Hong-Han
• Primary Examiner(s): KUO, WENSING W
• Application Number:
  US13/293,158
• Publication Number:
  US 20120052609A1
• Time in Patent Office: 691 Days
• Field of Search: 438/45
• US Class Current: 438/45
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A thin film transistor (TFT), including a substrate, a gate electrode on the substrate, an oxide semiconductor layer including a channel region, a source region, and a drain region, a gate insulating layer between the gate electrode and the oxide semiconductor layer, and source and drain electrodes in contact with the source and drain regions of the oxide semiconductor layer, respectively, wherein the oxide semiconductor layer has a GaInZnO (GIZO) bilayer structure including a lower layer and an upper layer, and the upper layer has a different indium (In) concentration than the lower layer.

Claims

1. A method of manufacturing a display device, comprising:

forming a thin film transistor, including;

forming a gate electrode on a substrate;

forming a gate insulating layer on the substrate having the gate electrode;

forming on the gate insulating layer an oxide semiconductor layer with a channel region, a source region and a drain region;

forming source and drain electrodes in contact with the source and drain regions of the oxide semiconductor layer, respectively,

wherein the forming of the oxide semiconductor layer includes;

depositing ions including In, Ga, and Zn from a target to form a lower layer on the gate insulating layer, and

forming an upper layer on the lower layer, the upper layer having an In concentration lower than the lower layer, and

providing a display panel with the thin film transistor.

2. The method as claimed in claim 1, wherein the In concentration of the lower layer is about 40 to about 60 at. %, and the In concentration of the upper layer is about 30 to about 50 at. %.

3. The method as claimed in claim 1, wherein the target includes an InGaZnO target and an InZnO target.

4. The method as claimed in claim 3, wherein, during forming the lower layer and upper layer, the In concentration in the upper layer is altered by adjusting the amplitude of the bias power applied to the respective InGaZnO and InZnO targets.

5. The method as claimed in claim 3, wherein, during forming the lower layer and upper layer, the In concentration in the upper layer is altered by adjusting the intensity of a pulse laser irradiating the respective InGaZnO and InZnO targets.

6. The method as claimed in claim 3, wherein, during forming the lower layer and upper layer, the In concentration is altered by adjusting the molar ratio of In in the InGaZnO and InZnO targets.