Semiconductor device and method for manufacturing the same

• US 8,546,182 B2
• Filed: 11/19/2012
• Issued: 10/01/2013
• Est. Priority Date: 11/28/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Akimoto, Kengo, Sasaki, Toshinari, Kuwabara, Hideaki
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/680,349
• Publication Number:
  US 20130078762A1
• Time in Patent Office: 316 Days
• Field of Search: 257/9, 257/66, 257/72, 257/E33.019, 257/E21.459, 257/E29.296, 438/104, 438/158
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a first non-single crystalline oxide semiconductor film over a substrate by sputtering, the first non-single crystalline oxide semiconductor film including a region to become a channel region of a transistor;

forming a second non-single crystalline oxide semiconductor film over the first non-single crystalline oxide semiconductor film by sputtering, the second non-single crystalline oxide semiconductor film having a lower conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming an insulating film on the second oxide semiconductor layer,

wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film comprises indium and oxygen.

5. The method according to claim 1, wherein the first non-single crystalline oxide semiconductor film is formed over a gate electrode.

6. The method according to claim 1, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

7. The method according to claim 1, wherein a carrier concentration of the first non-single crystalline oxide semiconductor film is lower than 1×

10¹⁷/cm³.

8. The method according to claim 1, wherein the conductivity of the second non-single crystalline oxide semiconductor film is 1×

10<sup>−

8</sup> S/cm or lower.

9. The method according to claim 1, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor film is 5×

10¹⁹/cm³ or lower.

25. The method according to claim 1, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film is formed by DC sputtering.

2. A method of manufacturing a semiconductor device comprising the steps of:

performing first sputtering to form a first non-single crystalline oxide semiconductor film over a substrate, the first non-single crystalline oxide semiconductor film including a region to become a channel region of a transistor;

performing second sputtering to form a second non-single crystalline oxide semiconductor film over the first non-single crystalline oxide semiconductor film, the second non-single crystalline oxide semiconductor film having a lower conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming an insulating film on the second oxide semiconductor layer,

wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film comprises indium and oxygen.

10. The method according to claim 2, wherein the first non-single crystalline oxide semiconductor film is formed over a gate electrode.

11. The method according to claim 2, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

12. The method according to claim 2, wherein a carrier concentration of the first non-single crystalline oxide semiconductor film is lower than 1×

10¹⁷/cm³.

13. The method according to claim 2, wherein the conductivity of the second non-single crystalline oxide semiconductor film is 1×

10<sup>−

8</sup> S/cm or lower.

14. The method according to claim 2, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor film is 5×

10¹⁹/cm³ or lower.

3. A method of manufacturing a semiconductor device comprising the steps of:

forming a first non-single crystalline oxide semiconductor film over a substrate by sputtering in a first sputtering chamber, the first non-single crystalline oxide semiconductor film including a region to become a channel region of a transistor;

forming a second non-single crystalline oxide semiconductor film over the first non-single crystalline oxide semiconductor film by sputtering successively after forming the first non-single crystalline oxide semiconductor film without exposing the first non-single crystalline oxide semiconductor film to air, the second non-single crystalline oxide semiconductor film having a lower conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

forming an insulating film on the second oxide semiconductor layer,

wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film comprises indium and oxygen.

15. The method according to claim 3, wherein the first non-single crystalline oxide semiconductor film is formed over a gate electrode.

16. The method according to claim 3, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

17. The method according to claim 3, wherein a carrier concentration of the first non-single crystalline oxide semiconductor film is lower than 1×

10¹⁷/cm³.

18. The method according to claim 3, wherein the conductivity of the second non-single crystalline oxide semiconductor film is 1×

10<sup>−

8</sup> S/cm or lower.

19. The method according to claim 3, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor film is 5×

10¹⁹/cm³ or lower.

4. A method of manufacturing a semiconductor device comprising the steps of:

forming a first non-single crystalline oxide semiconductor film over a substrate by sputtering, the first non-single crystalline oxide semiconductor film including a region to become a channel region of a transistor;

forming a second non-single crystalline oxide semiconductor film over the first non-single crystalline oxide semiconductor film by sputtering, the second non-single crystalline oxide semiconductor film having a lower conductivity than the first non-single crystalline oxide semiconductor film;

etching the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film to form a first oxide semiconductor layer and a second oxide semiconductor layer on the first oxide semiconductor layer;

heating the first oxide semiconductor layer and the second oxide semiconductor layer at a temperature of 200°

C. to 600°

C.;

forming an insulating film on the second oxide semiconductor layer,

wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film comprises indium and oxygen.

20. The method according to claim 4, wherein the first non-single crystalline oxide semiconductor film is formed over a gate electrode.

21. The method according to claim 4, wherein each of the first non-single crystalline oxide semiconductor film and the second non-single crystalline oxide semiconductor film further comprises gallium and zinc.

22. The method according to claim 4, wherein a carrier concentration of the first non-single crystalline oxide semiconductor film is lower than 1×

10¹⁷/cm³.

23. The method according to claim 4, wherein the conductivity of the second non-single crystalline oxide semiconductor film is 1×

10<sup>−

8</sup> S/cm or lower.

24. The method according to claim 4, wherein a concentration of sodium in the first non-single crystalline oxide semiconductor film is 5×

10¹⁹/cm³ or lower.