Semiconductor device and fabricating method thereof

• US 8,546,212 B2
• Filed: 12/21/2011
• Issued: 10/01/2013
• Est. Priority Date: 12/21/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Su, Hao, Hu, Hang, Liao, Hong
• Primary Examiner(s): Lee, Kyoung
• Application Number:
  US13/332,392
• Publication Number:
  US 20130161754A1
• Time in Patent Office: 650 Days
• Field of Search: None
• US Class Current: 438/216
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar

Abstract

A manufacturing method of a semiconductor device includes the following steps. First, a substrate is provided. At least one gate trench and a first inter-layer dielectric layer are formed on the substrate. A work function metallic layer is then formed in the gate trench. A first contact hole is then formed in the first inter-layer dielectric layer. A main conductive layer is formed in the gate trench and the first contact hole simultaneously.

Claims

1. A manufacturing method of a semiconductor device, comprising:

providing a substrate having at least a first semiconductor unit, at least a second semiconductor unit and a first ILD layer formed thereon, wherein the first semiconductor unit has a first sacrificial gate structure formed therein, the second semiconductor unit has a second sacrificial gate structure formed therein, and the first ILD layer is formed on the substrate; and

forming a first gate trench in the first sacrificial gate structure; and

forming a second gate trench in the second sacrificial gate structure; and

forming a first metal layer on the surface of the first gate trench and the second gate trench; and

forming a plurality of first contact holes in the first metal layer and the first ILD layer; and

forming a second metal layer in the first gate trench, the second gate trench and the first contact hole simultaneously.

2. The manufacturing method of the semiconductor device of claim 1, wherein a conductive type of the first semiconductor is an n-type and a conductive type of the second semiconductor is a p-type.

3. The manufacturing method of the semiconductor device of claim 1, wherein the first metal layer comprises a second work function metal layer.

4. The manufacturing method of the semiconductor device of claim 1, wherein the second metal layer comprises a main conductive layer.

5. The manufacturing method of the semiconductor device of claim 1, further comprising forming a first work function metal layer in the second gate trench before forming the first work function metal layer.

6. The manufacturing method of the semiconductor device of claim 1, wherein a high-k gate dielectric layer formed in the first gate sacrificial structure and the second gate sacrificial structure, and the high-k gate dielectric layer is formed between the substrate and the first gate layer.

7. The manufacturing method of the semiconductor device of claim 3, wherein the first contact hole may be formed after the second work function metal layer is formed.

8. The manufacturing method of the semiconductor device of claim 5, wherein the first contact hole may be formed after the first work function metal layer is formed.

9. The manufacturing method of the semiconductor device of claim 6, wherein the high dielectric constant (high-k) dielectric layer has a “

−

”

or “

U”

shaped profile structure.

10. A semiconductor device, comprising:

a substrate;

a first semiconductor unit and a second semiconductor unit disposed on the substrate, wherein the first semiconductor unit comprises a first metal gate structure, and the second semiconductor unit comprises a second metal gate structure;

a first ILD layer disposed on the substrate, and;

a plurality of contact holes, formed in the ILD layer, wherein the first metal gate structure and the second metal gate structure comprise a second work function metal layer and a main conductive layer; and

the contact holes comprise the main conductive layer, wherein the main conductive layer is directly connected to the sidewalls of the first contact holes.

11. The semiconductor device of claim 10, wherein the contact holes do not comprise the second work function metal layer.

12. The semiconductor device of claim 10, wherein the second metal gate structure further comprises a first work function metal layer disposed between the second work function metal layer and the substrate.

13. The semiconductor device of claim 10, wherein a conductive type of the first semiconductor unit is an n-type and a conductive type of the second semiconductor unit is a p-type.

14. The semiconductor device of claim 10, wherein both the first semiconductor unit and the second semiconductor unit comprise a high-k gate dielectric layer.