Methods of fabricating a memory device

• US 8,546,215 B2
• Filed: 03/01/2013
• Issued: 10/01/2013
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Haller, Gordon, Tang, Sanh Dang, Cummings, Steve
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): PRASAD, NEIL R
• Application Number:
  US13/781,862
• Publication Number:
  US 20130178025A1
• Time in Patent Office: 214 Days
• Field of Search: 438/242, 438/288, 438/972, 438/253, 257/E21.646
• US Class Current: 438/253
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/318 the storage electrode having multiple segments
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/485 Bit line contacts

Abstract

A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

Claims

1. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming a conductive data line over the second source/drain region and which electrically connects to the second source/drain region; and

forming a nitride-comprising cap over that portion of the conductive data line that is over the second source/drain region, the nitride-comprising cap extending laterally beyond sidewalls of the conductive data line over the second source/drain region.

2. The method of claim 1 comprising forming silicon dioxide over the nitride-comprising cap, the silicon dioxide extending laterally beyond sidewalls of the nitride cap.

3. The method of claim 2 comprising forming insulative spacers that are laterally over the sidewalls of the nitride-comprising cap, the silicon dioxide being elevationally over the insulative spacers.

4. The method of claim 1 wherein the conductive data line electrically and directly physically contacts the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.

5. The method of claim 1 comprising forming the first and second source/drain regions to have coplanar upper surfaces in the completed construction of the memory device.

6. The method of claim 1 comprising forming the charge storage device to comprise a capacitor.

7. The method of claim 1 comprising forming an upper surface of the gate to be elevationally below upper surfaces of each of the first and second source/drain regions.

8. The method of claim 7 comprising forming the upper surface of the gate to be elevationally closer to a lower surface of the second source/drain region than to the second source/drain region upper surface in the completed construction of the memory device.

9. The method of claim 1 comprising forming an upper surface of the gate to be elevationally closer to lower surfaces of each of the first and second source/drain regions than to an upper surface of the semiconductive material.

10. A method of fabricating a memory device, the method comprising;

forming a recessed gate within semiconductive material;

forming a first source/drain region and a second source/drain region adjacent opposing lateral sides of the recessed gate, wherein application of a voltage to the gate results in the formation of a conductive channel between the first and second source/drain regions along a path that is within the semiconductive material;

forming a charge storage device above the semiconductive material, wherein the charge storage device is electrically coupled to the first source/drain region;

forming dielectric material over the second source/drain region;

patterning and etching the dielectric material to expose only a portion of the second/source drain region; and

forming a conductive data line which electrically connects to the second source/drain region.

11. The method of claim 10 wherein the exposed portion is spaced from opposing lateral sides of the second source/drain region.

12. The method of claim 11 wherein the exposed portion is centered relative to the opposing lateral sides of the second source/drain region.

13. The method of claim 10 wherein the exposed portion is over a lateral center of the second source/drain region.

14. The method of claim 10 comprising forming insulative spacers that are laterally over sidewalls of the conductive data line.

15. The method of claim 10 wherein the conductive data line is formed over the second source/drain region, and forming a nitride-comprising cap over a portion of the conductive data line that is over the second source/drain region, the nitride-comprising cap extending laterally beyond sidewalls of the conductive data line over the second source/drain region.

16. The method of claim 10 comprising forming the charge storage device to comprise a container-shaped capacitor.

17. The method of claim 10 wherein the conductive data line electrically and directly physically contacts the second source/drain region in the absence of any separately formed conductive plug extending between the second source/drain region and the conductive data line in a completed construction of the memory device.

18. The method of claim 10 comprising forming the conductive data line to comprise polysilicon.

19. The method of claim 10 comprising forming the conductive data line to comprise silicide.

20. The method of claim 10 comprising forming the conductive data line to comprise polysilicon and silicide.