Strained thin body CMOS device having vertically raised source/drain stressors with single spacer

• US 8,546,228 B2
• Filed: 06/16/2010
• Issued: 10/01/2013
• Est. Priority Date: 06/16/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., Cheng, Kangguo, Khakifirooz, Ali, Kulkarni, Pranita, Shahidi, Ghavam G.
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US12/816,399
• Publication Number:
  US 20110309446A1
• Time in Patent Office: 1,203 Days
• Field of Search: 438/300, 438/163, 438/149, 438/154, 257/351, 257/377, 257/E21.619
• US Class Current: 438/300
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

Claims

1. A method of forming a transistor device, the method comprising:

forming a patterned gate structure over an extremely thin silicon-on-insulator (ETSOI) semiconductor substrate having a thickness on the order of about 10 nanometers (nm) or less;

forming a spacer layer over the ETSOI semiconductor substrate and patterned gate structure;

removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and

forming a vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the vertical sidewall spacer by epitaxially growing a silicon carbon (Si;

C) semiconductor material on the ETSOI substrate and in-situ doping the semiconductor material with an n-type material, wherein the RSD structure abuts the vertical sidewall spacer and produces a tensile strain on a channel region of the ETSOI semiconductor substrate below the patterned gate structure.

2. The method of claim 1, wherein the n-type material comprises phosphorous (P).

3. The method of claim 1, further comprising performing an anneal to as to diffuse dopant material from the RSD structure into the channel region, forming a source/drain extension.

4. The method of claim 3, further comprising forming a silicide layer over the RSD structure and the patterned gate structure, with the vertical sidewall profile of the RSD structure adjacent the vertical sidewall spacer sufficient to prevent the silicide layer from encroaching into the channel region.

5. A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising:

forming a first patterned gate structure over an extremely thin silicon-on-insulator (ETSOI) semiconductor substrate corresponding to a first polarity type transistor region, and forming a second patterned gate structure over the ETSOI semiconductor substrate corresponding to a second polarity type transistor region, the ETSOI semiconductor substrate having a thickness on the order of about 10 nanometers (nm) or less;

forming a spacer layer over the ETSOI semiconductor substrate and the first and patterned gate structures;

removing horizontally disposed portions of the spacer layer in the first polarity type transistor region so as to form a vertical sidewall spacer adjacent the first patterned gate structure;

forming a first type vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the vertical sidewall spacer of the first patterned gate structure, wherein the first type RSD structure abuts the vertical sidewall spacer of the first patterned gate structure and produces one of a compressive and a tensile strain on a channel region of the ETSOI semiconductor substrate below the first patterned gate structure;

forming a protective hardmask over first and second polarity type transistor regions;

removing the protective hardmask and horizontally disposed portions of the spacer layer in the second polarity type transistor region so as to form a vertical sidewall spacer adjacent the second patterned gate structure;

forming a second type vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the vertical sidewall spacer of the second patterned gate structure, wherein the second type RSD structure abuts the vertical sidewall spacer of the second patterned gate structure and produces the other of a compressive and a tensile strain on a channel region of the ETSOI semiconductor substrate below the second patterned gate structure; and

removing the protective hardmask in the first polarity type transistor region.

6. The method of claim 5, wherein forming the first and second type RSD structures comprises epitaxially growing first and second semiconductor materials on the ETSOI semiconductor substrate and in-situ doping the first and second semiconductor materials.

7. The method of claim 6, wherein the first semiconductor material comprises silicon germanium (SiGe), the in-situ doping is a p-type material, and the first type RSD structure produces a compressive stress on the channel region.

8. The method of claim 7, wherein the p-type material comprises boron (B).

9. The method of claim 6, wherein the second semiconductor material comprises silicon carbon (Si:

C), the in-situ doping is an n-type material, and the second type RSD structure produces a tensile stress on the channel region.

10. The method of claim 9, wherein the n-type material comprises phosphorous (P).

11. The method of claim 6, further comprising performing an anneal to as to diffuse dopant material from the RSD structure into the channel regions, forming a source/drain extension.

12. The method of claim 11, further comprising forming a silicide layer over the first and second type RSD structures and the first and second patterned gate structures, with the vertical sidewall profiles of the first and second type RSD structures adjacent the vertical sidewall spacers sufficient to prevent the silicide layer from encroaching into the channel regions.