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Strained thin body CMOS device having vertically raised source/drain stressors with single spacer

  • US 8,546,228 B2
  • Filed: 06/16/2010
  • Issued: 10/01/2013
  • Est. Priority Date: 06/16/2010
  • Status: Active Grant
First Claim
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1. A method of forming a transistor device, the method comprising:

  • forming a patterned gate structure over an extremely thin silicon-on-insulator (ETSOI) semiconductor substrate having a thickness on the order of about 10 nanometers (nm) or less;

    forming a spacer layer over the ETSOI semiconductor substrate and patterned gate structure;

    removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and

    forming a vertical sidewall profile raised source/drain (RSD) structure atop the ETSOI semiconductor substrate and adjacent the vertical sidewall spacer by epitaxially growing a silicon carbon (Si;

    C) semiconductor material on the ETSOI substrate and in-situ doping the semiconductor material with an n-type material, wherein the RSD structure abuts the vertical sidewall spacer and produces a tensile strain on a channel region of the ETSOI semiconductor substrate below the patterned gate structure.

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