Integrated circuits including metal-insulator-metal capacitors and methods of forming the same

• US 8,546,235 B2
• Filed: 05/05/2011
• Issued: 10/01/2013
• Est. Priority Date: 05/05/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Sung-Hui, Liu, Yuan-Hung, Chen, Ming-Fa
• Primary Examiner(s): SMITH, BRADLEY
• Application Number:
  US13/101,788
• Publication Number:
  US 20120280358A1
• Time in Patent Office: 880 Days
• Field of Search: 438/393, 438/394
• US Class Current: 438/394
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

Claims

1. An integrated circuit comprising:

a substrate;

a first metal-insulator-metal (MIM) capacitor disposed over the substrate, the MIM capacitor comprising;

a first metallic capacitor plate disposed over the substrate;

at least one first insulator layer disposed over the first metallic capacitor plate; and

a second metallic capacitor plate disposed over the at least one first insulator layer; and

at least one first dielectric layer, wherein at least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer;

wherein the at least one first dielectric layer includes a first portion and a second portion, the first portion is between the first metallic capacitor plate and the at least one first insulator layer, the second portion is not covered by the at least one first insulator layer, and the first portion is thicker than the second portion.

2. The integrated circuit of claim 1, wherein an edge of the at least one first dielectric layer under the at least one first insulator layer is separated from an edge of the at least one first insulator layer by a distance of about 1,000 Å

or less.

3. The integrated circuit of claim 1, wherein an etching selectivity of the at least one first dielectric layer is different from that of the at least one first insulator layer.

4. The integrated circuit of claim 1, wherein the at least one first insulator includes at least one material having a dielectric constant that is larger than 3.9.

5. The integrated circuit of claim 1, further comprising:

a metallic resistor disposed over the substrate, wherein the metallic resistor having a thickness same as the first metallic capacitor plate.

6. An integrated circuit comprising:

a substrate;

a first metal-insulator-metal (MIM) capacitor disposed over the substrate, the MIM capacitor comprising;

a first metallic capacitor plate disposed over the substrate;

at least one first insulator layer disposed over the first metallic capacitor plate; and

a second metallic capacitor plate disposed over the at least one first insulator layer;

at least one first dielectric layer, wherein at least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer; and

a metallic resistor disposed over the substrate, wherein the metallic resistor having a metallic material as same as the first metallic capacitor plate.

7. The integrated circuit of claim 6, further comprising:

a second MIM capacitor, wherein the second MIM capacitor comprises;

the second metallic capacitor plate;

at least one second insulator layer disposed over the second metallic capacitor plate; and

a third metallic capacitor plate disposed over the at least one second insulator layer; and

at least one second dielectric layer, wherein at least a portion of the at least one second dielectric layer is disposed between the second metallic capacitor plate and the at least one second insulator layer.

8. The integrated circuit of claim 7, wherein an edge of the at least one second dielectric layer under the at least one second insulator layer is separated from an edge of the at least one second insulator layer by a distance of about 1,000 Å

or less.

9. The integrated circuit of claim 7, wherein an etching selectivity of the at least one second dielectric layer is different from that of the at least one second insulator layer.

10. The integrated circuit of claim 7, wherein the at least one second dielectric layer includes a first portion and a second portion, the first portion is between the second metallic capacitor plate and the at least one second insulator layer, the second portion is not covered by the at least one second insulator layer, and the first portion is thicker than the second portion.

11. An integrated circuit comprising:

a substrate;

a first metal-insulator-metal (MIM) capacitor disposed over the substrate, the MIM capacitor comprising;

a first metallic capacitor plate disposed over the substrate;

at least one first insulator layer disposed over the first metallic capacitor plate; and

a second metallic capacitor plate disposed over the at least one first insulator layer;

at least one first dielectric layer, wherein the at least one first dielectric layer includes a first portion and a second portion, the first portion is between the first metallic capacitor plate and the at least one first insulator layer, the second portion is not covered by the at least one first insulator layer, and the first portion is thicker than the second portion; and

a metallic resistor disposed over the substrate, wherein the metallic resistor having a metallic material as same as the first metallic capacitor plate.

12. The integrated circuit of claim 11, wherein an edge of the at least one first dielectric layer under the at least one first insulator layer is separated from an edge of the at least one first insulator layer by a distance of about 1,000 Å

A or less.

13. The integrated circuit of claim 11, further comprising:

a second MIM capacitor, wherein the second MIM capacitor comprises;

the second metallic capacitor plate;

at least one second insulator layer disposed over the second metallic capacitor plate; and

a third metallic capacitor plate disposed over the at least one second insulator layer; and

at least one second dielectric layer, wherein at least a portion of the at least one second dielectric layer is disposed between the second metallic capacitor plate and the at least one second insulator layer.

14. The integrated circuit of claim 13, wherein the at least one second dielectric layer includes a first portion and a second portion, the first portion is between the second metallic capacitor plate and the at least one second insulator layer, the second portion is not covered by the at least one second insulator layer, and the first portion is thicker than the second portion.

15. A method of forming an integrated circuit, the method comprising:

forming a first metallic material over a substrate;

forming at least one first dielectric layer over the first metallic material;

forming at least one first insulator material over the at least one first dielectric layer;

forming a second metallic material over the at least one first insulator material;

removing portions of the second metallic material and the at least one first insulator material so as to form a first metallic capacitor plate and at least one first insulator layer of a first MIM capacitor, wherein the removal process uses the at least one first dielectric layer as an etch stop layer; and

removing a portion of the first metallic material so as to form a second metallic capacitor plate of the first MIM capacitor.

16. The method of claim 15, wherein removing portions of the second metallic material and the at least one first insulator material has an etching rate to the at least one first insulator layer that is larger than that to the at least one first dielectric layer.

17. The method of claim 15, wherein the at least one first insulator layer covers at least a portion of the at least one first dielectric layer.

18. The method of claim 15, wherein removing portions of the second metallic material and the at least one first insulator material includes removing a top portion of the at least one first dielectric layer.

19. The method of claim 15, wherein removing a portion of the first metallic material comprises defining a metallic resistor over the substrate.

20. The method of claim 15, further comprising:

forming at least one second dielectric layer over the first metallic capacitor plate;

forming at least one second insulator material over the at least one second dielectric layer;

forming a third metallic material over the at least one second insulator material; and

removing portions of the third metallic material and the at least one second insulator material so as to form a third metallic capacitor plate and at least one second insulator layer of a second MIM capacitor, wherein the removal process uses the at least one second dielectric layer as an etch stop layer.