Metal gate FET having reduced threshold voltage roll-off

• US 8,546,252 B2
• Filed: 10/05/2009
• Issued: 10/01/2013
• Est. Priority Date: 10/05/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Anderson, Brent A., Nowak, Edward J., Rankin, Jed H.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US12/573,440
• Publication Number:
  US 20110079828A1
• Time in Patent Office: 1,457 Days
• Field of Search: 438/592, 438/183, 438/199, 438/270, 438/275, 438/561, 438/587, 438/595
• US Class Current: 438/592
• CPC Class Codes: H01L 21/28079 the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28105 the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A structure and method to create a metal gate having reduced threshold voltage roll-off. A method includes: forming a gate dielectric material on a substrate; forming a gate electrode material on the gate dielectric material; and altering a first portion of the gate electrode material. The altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

Claims

1. A method of forming a semiconductor structure using a replacement gate process, comprising:

forming a gate dielectric material on a substrate;

forming a gate electrode material on the gate dielectric material;

forming a mandrel on the gate electrode material;

forming a dielectric material at sides of the mandrel;

removing the mandrel to form a trench;

forming an additional layer of the gate electrode material in the trench;

forming a second gate electrode material on the additional layer of the gate electrode material; and

altering a first portion of the gate electrode material,

wherein the altering causes the first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

2. The method of claim 1, wherein the second gate electrode material is different than the gate electrode material, and

the altering comprises diffusing the second gate electrode material into the first portion of the gate electrode material.

3. The method of claim 2, further comprising thinning the additional layer of the gate electrode material before the filling the trench with the second gate electrode material.

4. The method of claim 3, wherein the thinning causes the additional layer of the gate electrode material to have a vertical height that is less than a lateral thickness of a sidewall portion of the gate electrode material.

5. A method of forming a semiconductor structure, comprising:

forming a gate dielectric material on a substrate;

forming a gate electrode material on the gate dielectric material;

forming a barrier layer over the gate electrode material;

thinning a second portion of the barrier layer relative to a first portion of the barrier layer;

forming a metal replacement gate material on exposed surfaces of the barrier layer in a trench defined by the barrier layer; and

diffusing ions from the metal replacement gate material into the gate electrode material, wherein the diffusing causes a first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

6. The method of claim 5, wherein the diffusing comprises:

diffusing a first amount of the metal replacement gate material through the first portion of the barrier layer into the first portion of the gate electrode material, and

diffusing a second amount of the metal replacement gate material through the second portion of the barrier layer into the second portion of the gate electrode material.

7. The method of claim 6, wherein the second amount is different than the first amount due to the thinning.

8. The method of claim 5, wherein the thinning comprises:

masking the first portion of the barrier layer, and

etching the second portion of the barrier layer.

9. The method of claim 5, wherein the thinning comprises:

performing an angled ion-implant of the barrier layer such that ions are implanted in the second portion of the barrier layer, and

simultaneously etching the first and second portions of the barrier layer.

10. The method of claim 5, wherein the first and second portions of the gate electrode material provide an asymmetric work function for a FET comprising the metal replacement gate material.

11. A method of forming a semiconductor structure, comprising:

forming a gate dielectric material on a substrate;

forming a gate electrode material on the gate dielectric material;

forming a diffusing material on the gate electrode material and on sidewalls of a gate trench containing the gate electrode material;

forming a barrier layer on the diffusing material;

forming a gate conductor in a trench defined by the barrier layer;

annealing the semiconductor structure, wherein the annealing causes diffusion from the diffusing material into the gate electrode material, and wherein the diffusion causes a first portion of the gate electrode material to have a first work function that is different than a second work function associated with a second portion of the gate electrode material.

18. The method of claim 11, wherein:

the first portion of the gate electrode material includes lateral edges of the gate electrode material; and

the second portion of the gate electrode material includes a central portion of the gate electrode material.

12. A method of forming a semiconductor structure, comprising:

forming a gate dielectric material on a substrate;

forming a first layer of a gate electrode material on the gate dielectric material;

forming a mandrel on the first layer of the gate electrode material;

forming an interlevel dielectric layer on the substrate and at sides of the mandrel;

removing the mandrel, wherein the removing forms a gate trench defined by the interlevel dielectric layer, and wherein the removing exposes a surface of the first layer of the gate electrode material;

forming an additional layer of the gate electrode material on the surface of the first layer of the gate electrode material and on sidewalls of the gate trench;

removing a first portion of the first layer of the gate electrode material and the additional layer of the gate electrode material from atop a first portion of the gate dielectric material; and

forming a conductive material on the first portion of the gate dielectric material,

wherein a second portion of the first layer of the gate electrode material and the additional layer of the gate electrode material remains on a second portion of the gate dielectric material after the removing,

the gate electrode material has a first work function,

the conductive material has a second work function different than the first work function, and

the removing comprises etching the first portion of the gate electrode material using an anisotropic etch.

16. The method of claim 12, wherein the anisotropic etch selectively etches the gate electrode material in a substantially vertical direction and leaves vertical columns of the gate electrode material on walls of the interlevel dielectric layer.

17. The method of claim 12, wherein the additional layer of the gate electrode material is formed directly on a top surface of the interlevel dielectric layer.

13. A method of forming a semiconductor structure, comprising:

forming a gate dielectric material on a substrate;

forming a gate electrode material on the gate dielectric material and on sidewalls of a gate trench;

forming a first reacting material on a first portion of the gate electrode material;

forming a second reacting material on a second portion of the gate electrode material, wherein the second reacting material is composed of a different material than the first reacting material; and

creating a non-uniform work function in the gate electrode material.

14. The method of claim 13, wherein the creating the non-uniform work function comprises annealing the semiconductor structure to diffuse the first reacting material and the second reacting material into regions of the gate electrode material.

15. The method of claim 14, wherein the forming the first reacting material on the first portion of the gate electrode material comprises:

conformally depositing a layer of the first reacting material on horizontal and vertical surfaces of the gate electrode material; and

removing the first reacting material from the horizontal surfaces of the gate electrode material.

19. The method of claim 13, wherein the first reacting material comprises lanthanum and the second reacting material comprises aluminum.