Charging protection device

• US 8,546,855 B2
• Filed: 09/22/2011
• Issued: 10/01/2013
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zhou, Jingrong, Wu, David, Buller, James F.
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/239,865
• Publication Number:
  US 20120007182A1
• Time in Patent Office: 740 Days
• Field of Search: 257/79, 257/347, 257/288, 257/607, 257/656, 257/E21.042, 257/E21.051, 257/E21.32, 257/E21.352, 257/E21.311, 257/E21.37, 257/E21.55, 257/E21.546
• US Class Current: 257/288
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P⁺ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P⁺-doped substrate contact in the bulk silicon layer of the SOI substrate.

Claims

1. A semiconductor device comprising:

a silicon-on-insulator (SOI) substrate including a bulk silicon layer;

an active silicon layer on the SOI substrate;

a transistor formed in the active silicon layer, the transistor including source/drain regions; and

a diode formed in the active silicon layer, the diode including two active regions;

first, second, third, and fourth conductive contacts;

first and second metal lines;

wherein the first conductive contact connects the drain of the transistor with the first metal line, the second conductive contact connects one active region of the diode with the first metal line, the third conductive contact connects the second active region of the diode with the second metal line, and the fourth conductive contact connects the second metal line to the bulk silicon layer;

wherein, the drain region, active diode regions, and bulk silicon layer are electrically connected to form a charging protection device.

2. The semiconductor device according to claim 1, further comprising a shallow trench isolation region between the transistor and the diode.

3. The semiconductor device according to claim 1, wherein the bulk silicon layer is P-doped.

4. The semiconductor device according to claim 3, further comprising a P⁺-doped substrate contact formed in the bulk silicon layer and connected to the fourth conductive contact.

5. The semiconductor device according to claim 4, wherein the transistor is an NMOS transistor .

6. The semiconductor device according to claim 4, wherein the first active region of the diode is N⁺-doped and the second active region is P⁺-doped.

7. The semiconductor device according to claim 4, wherein the first active region of the diode is P⁺-doped and the second active region is N⁺-doped.

8. The semiconductor device according to claim 4, wherein the first, second, third, and fourth conductive contacts comprise tungsten or polysilicon.

9. The semiconductor device according to claim 4, further comprising an interlayer dielectric on the transistor and the diode, wherein the first, second, third, and fourth conductive contacts are formed through the interlayer dielectric and the first and second metal lines are formed on the interlayer dielectric.

10. The semiconductor device according to claim 9, further comprising a metal 1 pattern on the interlayer dielectric, wherein the metal 1 pattern includes the first and second metal lines.