Semiconductor device incorporating charge balancing

• US 8,546,878 B2
• Filed: 06/09/2011
• Issued: 10/01/2013
• Est. Priority Date: 01/09/2007
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): Weiss, Howard
• Assistant Examiner(s): Jahan, Bilkis
• Application Number:
  US13/156,848
• Publication Number:
  US 20120161226A1
• Time in Patent Office: 845 Days
• Field of Search: 257/330, 257/228, 257/229, 257/341, 257/335, 257/E29.027, 257/E29.066, 257/E29.256
• US Class Current: 257/335
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02321 introduction of substances into an already existing insulating layer H01L21/02227 and subgroups take precedence
• CPC Class Codes: H01L 21/2003 characterised by the substrate
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 : Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 : Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/408 : with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/66537 : using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66666 : Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 : having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

a semiconductor layer of a second conductivity type formed on the semiconductor layer of the first conductivity type, wherein the semiconductor layer of the second conductivity type is characterized by a first thickness;

a body layer of the second conductivity type extending a first predetermined distance into the semiconductor layer of the second conductivity type;

a plurality of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type, wherein each of the plurality of trenches comprises a first dielectric material disposed therein, the first dielectric material including an intentionally introduced charge;

a plurality of control gates coupled to the semiconductor layer of the second conductivity type; and

a plurality of source regions of the first conductivity type coupled to the semiconductor layer of the second conductivity type; and

wherein the intentionally introduced charge comprises a spatially fixed charge;

the intentionally introduced charge comprises a net positive charge associated with cesium ions;

the dielectric material comprises a silicon oxide material;

wherein a pair of termination trenches extending through the body layer of the second conductivity type and the semiconductor layer of the second conductivity type.

2. The semiconductor device of claim 1 wherein the intentionally introduced charge comprises a net negative charge associated with at least iodine, bromine, chromium, aluminum, or chlorine ions.

3. The semiconductor device of claim 1 wherein the second predetermined distance is greater than the first thickness.

4. The semiconductor device of claim 1 further comprising a third dielectric material disposed on the plurality of trenches and the plurality of control gates.

5. The semiconductor device of claim 1 wherein the second predetermined distance is less than the first thickness.

6. The semiconductor device of claim 1 wherein each of the plurality of control gates comprises a control gate trench extends a third predetermined distance through the body layer of the second conductivity type into the semiconductor layer of the second conductivity type.

7. The semiconductor device of claim 6 wherein the second predetermined distance and the third predetermined distance are substantially equal.

8. The semiconductor device of claim 6 wherein the control gate trench comprises a second dielectric material and a control gate material disposed interior to the second dielectric material.

9. The semiconductor device of claim 8 further comprising a third dielectric material disposed on the plurality of trenches and the plurality of control gates.

10. The semiconductor device of claim 8 wherein the control gate material comprises polysilicon.

11. A semiconductor device comprising:

an N-type semiconductor layer;

a P-type semiconductor layer formed on the N-type semiconductor layer, wherein the P-type semiconductor layer is characterized by a first thickness;

a P-type body layer extending a first predetermined distance into the P-type semiconductor layer;

a plurality of trenches extending a second predetermined distance into the P-type semiconductor layer, wherein each of the plurality of trenches comprises a first dielectric material disposed therein, the first dielectric material including an intentionally introduced charge;

wherein the intentionally introduced charge is sufficient to invert at least a portion of the P-type semiconductor layer;

a plurality of control gates coupled to the P-type semiconductor layer; and

a plurality of N-type source regions coupled to the P-type semiconductor layer; and

wherein the intentionally introduced charge comprises a net positive charge associated with cesium ions.

12. The semiconductor device of claim 11 wherein each of the plurality of control gates comprises a control gate trench extends a third predetermined distance through the P-type body layer into the P-type semiconductor layer.

13. The semiconductor device of claim 12 wherein the control gate trench comprises a second dielectric material and a control gate material disposed interior to the second dielectric material.

14. The semiconductor device of claim 13 further comprising a third dielectric material disposed on the plurality of trenches and the plurality of control gates.

15. The semiconductor device of claim 13 wherein the control gate material comprises polysilicon.