Controlling the device performance by forming a stressed backside dielectric layer

• US 8,546,886 B2
• Filed: 08/24/2011
• Issued: 10/01/2013
• Est. Priority Date: 08/24/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Lin, I-Ching
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/216,843
• Publication Number:
  US 20130049127A1
• Time in Patent Office: 769 Days
• Field of Search: 257/369, 257/E21.24, 257/E21.158, 257/E27.062
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate;

a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of the semiconductor substrate;

a first dielectric layer on a backside of the semiconductor substrate, wherein the first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device; and

a second dielectric layer on the backside of the semiconductor substrate, wherein the second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type, and wherein the second dielectric layer overlaps a second one of the PMOS device and the NMOS device.

2. The integrated circuit structure of claim 1, wherein each of the first and the second dielectric layers comprises silicon nitride.

3. The integrated circuit structure of claim 1, wherein the second dielectric layer comprises a portion extending over and contacting the first dielectric layer.

4. The integrated circuit structure of claim 1, wherein the first stress type is tensile, and the first one of the PMOS device and the NMOS device is the NMOS device.

5. The integrated circuit structure of claim 1, wherein the first stress type is compressive, and the first one of the PMOS device and the NMOS device is the PMOS device.

6. The integrated circuit structure of claim 1 further comprising:

a through-substrate via (TSV) in the semiconductor substrate; and

a metal pad on the backside of, and overlying, the semiconductor substrate, wherein the metal pad is electrically coupled to the TSV, wherein one of the first and the second dielectric layers comprises a portion over and overlapping an edge portion of the metal pad, and wherein a center portion of the metal pad is exposed through an opening in the one of the first and the second dielectric layers.

7. The integrated circuit structure of claim 1, wherein the first dielectric layer is overlying and overlapping substantially all MOS devices of a first conductivity type in a same chip as the PMOS device and the NMOS device, and is not overlapping substantially any of MOS devices of a second conductivity type in the same chip, and wherein the first and the second conductivity types are opposite conductivity types.

8. An integrated circuit structure comprising:

a semiconductor substrate;

a through-substrate via (TSV) extending from a back surface of the semiconductor substrate down to a front surface of the semiconductor substrate;

a metal pad on a backside of the semiconductor substrate and electrically coupled to the TSV;

a first dielectric layer over the back surface of the semiconductor substrate, wherein the first dielectric layer applies a first stress of a first stress type to the semiconductor substrate; and

a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer applies a second stress of a second stress type opposite the first stress type to the semiconductor substrate, and wherein one of the first and the second dielectric layers comprises a portion over and overlapping an edge portion of the metal pad, with a center portion of the metal pad exposed through an opening in the one of the first and the second dielectric layers.

9. The integrated circuit structure of claim 8, wherein each of the first and the second dielectric layers comprises silicon nitride.

10. The integrated circuit structure of claim 8 further comprising a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at the front surface of the semiconductor substrate, wherein the first dielectric layer is overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device, and wherein the second dielectric layer is overlapping a second one of the PMOS device and the NMOS device.

11. The integrated circuit structure of claim 10, wherein the second dielectric layer overlaps both the PMOS device and the NMOS device.

12. The integrated circuit structure of claim 10, wherein the first stress type is tensile, and the first one of the PMOS device and the NMOS device is the NMOS device.

13. The integrated circuit structure of claim 10, wherein the first stress type is compressive, and the first one of the PMOS device and the NMOS device is the PMOS device.

14. The integrated circuit structure of claim 10, wherein the first dielectric layer is overlying and overlapping substantially all MOS devices of a same conductivity type as the first one of the PMOS device and the NMOS device in a chip, and is not overlapping substantially any of MOS devices of a same conductivity type as the second one of the PMOS device and the NMOS device in the chip.

15. An integrated circuit structure comprising:

a semiconductor substrate;

a through-substrate via (TSV) extending from a back surface of the semiconductor substrate down to a front surface of the semiconductor substrate;

a metal pad on a backside of the semiconductor substrate and electrically coupled to the TSV;

a first passivation layer over the back surface of the semiconductor substrate, wherein the first passivation layer applies a first stress of a first stress type to the semiconductor substrate, and wherein the first passivation layer comprises;

a first portion covering edge portions of the metal pad, with a center portion of the metal pad exposed through an opening in the first passivation layer; and

a second portion level with the metal pad; and

a second passivation layer comprising a portion level with the first passivation layer, wherein the first and the second passivation layers are in contact with a same underlying layer, and wherein the second passivation layer applies a second stress of a second stress type opposite the first stress type to the semiconductor substrate.

16. The integrated circuit structure of claim 15, wherein each of the first and the second passivation layers comprises silicon nitride.

17. The integrated circuit structure of claim 15 further comprising a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at the front surface of the semiconductor substrate, wherein the first passivation layer is overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device, and wherein the second passivation layer overlaps both the PMOS device and the NMOS device.

18. The integrated circuit structure of claim 17, wherein the first stress type is tensile, and the first one of the PMOS device and the NMOS device is the NMOS device.

19. The integrated circuit structure of claim 17, wherein the first stress type is compressive, and the first one of the PMOS device and the NMOS device is the PMOS device.

20. The integrated circuit structure of claim 15, wherein the same underlying layer is a dielectric layer comprising:

a top surface in contact with the first passivation layer and the second passivation layer; and

a bottom surface in contact with a back surface of the semiconductor substrate.