3D integration microelectronic assembly for integrated circuit devices

• US 8,546,900 B2
• Filed: 06/09/2011
• Issued: 10/01/2013
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Optiz, Inc.
• Original Assignee: Optiz, Inc.
• Inventors: Oganesian, Vage
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/157,193
• Publication Number:
  US 20120313207A1
• Time in Patent Office: 845 Days
• Field of Search: 257/433, 257/737, 257/E31.117, 438/66
• US Class Current: 257/433
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/147 Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A microelectronic assembly for packaging/encapsulating IC devices, which includes a crystalline substrate handler having opposing first and second surfaces and a cavity formed into the first surface, a first IC device disposed in the cavity and a second IC device mounted to the second surface, and a plurality of interconnects formed through the crystalline substrate handler. Each of the interconnects includes a hole formed through the crystalline substrate handler from the first surface to the second surface, a compliant dielectric material disposed along the hole'"'"'s sidewall, and a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces. The compliant dielectric material insulates the conductive material from the sidewall. The second IC device, which can be an image sensor, is electrically coupled to the conductive materials of the plurality of interconnects. The first IC can be a processor for processing the signals from the image sensor.

Claims

1. A microelectronic assembly, comprising:

a crystalline substrate handler having opposing first and second surfaces, wherein a cavity is formed into the first surface that extends toward but does not reach the second surface;

a first IC device disposed in the cavity;

a second IC device mounted to the second surface;

a plurality of interconnects formed through the crystalline substrate handler, wherein each interconnect comprises;

a hole formed through the crystalline substrate handler with a sidewall extending between the first and second surfaces,

a compliant dielectric material disposed along the sidewall, and

a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces, wherein the compliant dielectric material insulates the conductive material from the sidewall;

wherein the second IC device is electrically coupled to the conductive materials of the plurality of interconnects.

2. The microelectronic assembly of claim 1, wherein the compliant dielectric material includes a polymer.

3. The microelectronic assembly of claim 1, wherein for each of the plurality of interconnects, the hole is tapered such that the hole has a smaller cross-sectional dimension at the second surface than at the first surface.

4. The microelectronic assembly of claim 1, wherein for each of the plurality of interconnects, the sidewall extends in a direction between 5°

and 35°

relative to a direction that is perpendicular to the first and second surfaces.

5. The microelectronic assembly of claim 1, wherein each of the plurality of interconnects further comprises:

a first bond pad disposed over the hole at the first surface and electrically coupled to the conductive material; and

a second bond pad disposed over the hole at the second surface and electrically coupled to the conductive material.

6. The microelectronic assembly of claim 5, wherein the second IC device is electrically coupled to the conductive materials of the plurality of interconnects by a plurality of wires that are electrically coupled to the second bond pads.

7. The microelectronic assembly of claim 1, wherein the second IC device is an image sensor and the first IC device is a processor for processing signals from the image sensor.

8. A microelectronic assembly, comprising:

a crystalline substrate handler having opposing first and second surfaces, wherein a cavity is formed into the first surface;

a first IC device disposed in the cavity;

a second IC device mounted to the second surface;

a plurality of interconnects formed through the crystalline substrate handler, wherein each interconnect comprises;

a hole formed through the crystalline substrate handler with a sidewall extending between the first and second surfaces,

a compliant dielectric material disposed along the sidewall, and

a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces, wherein the compliant dielectric material insulates the conductive material from the sidewall;

wherein the second IC device is electrically coupled to the conductive materials of the plurality of interconnects; and

one or more layers of insulation materials disposed on the first surface and extending across an opening of the cavity in the first surface that encapsulates the first IC device in the cavity.

9. The microelectronic assembly of claim 8, further comprising:

a plurality of bond pads electrically coupled to the first IC device and extending a least partially through the one or more layers of insulation materials.

10. The microelectronic assembly of claim 9, further comprising:

a plurality of rounded interconnects each electrically connected to one of the plurality bond pads.

11. A microelectronic assembly, comprising:

a crystalline substrate handler having opposing first and second surfaces, wherein a cavity is formed into the first surface;

a first IC device disposed in the cavity;

a second IC device mounted to the second surface;

a plurality of interconnects formed through the crystalline substrate handler, wherein each interconnect comprises;

a hole formed through the crystalline substrate handler with a sidewall extending between the first and second surfaces,

a compliant dielectric material disposed along the sidewall, and

a conductive material disposed along the compliant dielectric material and extending between the first and second surfaces, wherein the compliant dielectric material insulates the conductive material from the sidewall;

wherein the second IC device is electrically coupled to the conductive materials of the plurality of interconnects;

wherein the second IC device is an image sensor and the first IC device is a processor for processing signals from the image sensor; and

wherein the image sensor comprises an array of pixel sensors each including a photodetector for converting light energy to a voltage signal, and wherein the processor is configured to receive the voltage signals and to compute or interpolate color and brightness values for each of the voltage signals from the pixel sensors.