Stacked package including spacers and method of manufacturing the same

• US 8,546,938 B2
• Filed: 12/06/2011
• Issued: 10/01/2013
• Est. Priority Date: 02/15/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sang-Geun, Han, Dong-Chul, Goh, Seok, Kim, Jeong-Hoon
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US13/311,681
• Publication Number:
  US 20120205795A1
• Time in Patent Office: 665 Days
• Field of Search: 257/723, 257/724, 257/725, 257/E23.17, 257/E23.174, 257/E23.178
• US Class Current: 257/723
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15159 : Side view
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.

Claims

1. A stacked package comprising:

a first semiconductor package;

a second semiconductor package stacked on the first semiconductor package;

a molding member comprising a plurality of plug holes formed therein, each plug hole comprising a plug configured to electrically connect the first semiconductor package with the second semiconductor package; and

a plurality of spacers formed on an upper surface of the molding member and configured to prevent an electrical short between the plugs, the spacers interposed between the first semiconductor package and the second semiconductor package and supporting the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package.

2. The stacked package of claim 1, wherein the spacers are arranged at corners between the first semiconductor package and the second semiconductor package.

3. The stacked package of claim 1, wherein the spacers are configured to individually surround the plugs.

4. The stacked package of claim 1, wherein the spacers have a substantially same thickness.

5. The stacked package of claim 1, wherein each of the spacers has a rounded surface configured to contact with the second semiconductor package.

6. The stacked package of claim 1, wherein each of the spacers have a first surface that contacts the first semiconductor package, and a second surface that contacts the second semiconductor package and has an area smaller than that of the first surface.

7. The stacked package of claim 6, wherein each of the spacers has cross-sectional area that gradually decreases in a direction from the first surface toward to the second surface.

8. The stacked package of claim 1, wherein the spacers are disposed on the first semiconductor package.

9. The stacked package of claim 8, wherein the first semiconductor package comprises:

a first package substrate;

a first semiconductor chip disposed on a surface of the first package substrate that faces the second semiconductor package, the first semiconductor chip electrically connected with the first package substrate; and

a first molding member disposed on the surface of the first package substrate, the first molding member comprising the spacers and plug holes configured to receive the plugs.

10. The stacked package of claim 9, wherein the first semiconductor package further comprises conductive bumps interposed between the first package substrate and the first semiconductor chip to electrically connect the first package substrate with the first semiconductor chip.

11. The stacked package of claim 1, wherein the spacers are provided on the second semiconductor package.

12. The stacked package of claim 11, wherein the second semiconductor package comprises:

a second package substrate disposed on the first semiconductor package and electrically connected to the plugs, the second package substrate comprising the spacers;

a second semiconductor chip disposed on a surface of the second package substrate facing away from the first semiconductor package when the second semiconductor package is disposed on the first semiconductor package, the second semiconductor chip electrically connected with the second package substrate; and

a second molding member disposed on the surface of the second package substrate.

13. The stacked package of claim 1, wherein the spacers are provided on both the first semiconductor package and the second semiconductor package.

19. The stacked package of claim 1, wherein a number of the spacers is less than a number of the plugs.

14. A method of manufacturing a stacked package, the method comprising:

preparing a first package substrate;

arranging plugs on the first package substrate;

forming a first molding member on a surface of the first package substrate;

forming spacers on an upper surface of the first molding member; and

stacking a second semiconductor package on the first package substrate, the second semiconductor package electrically connected with the first package substrate via the plugs, and the spacers interposed between the first package substrate and the second semiconductor package to support the second semiconductor package to form a gap between the first package substrate and the second semiconductor package.

15. The method of claim 14, wherein preparing the first package substrate comprises:

arranging a first semiconductor chip on the surface of the first package substrate.

16. The method of claim 14, further comprising after forming the first molding member:

forming plug holes in the first molding member.

17. The method of claim 16, wherein the plug holes are formed by partially removing a surface of the first molding member to expose the plugs using a drill process or an etching process.

18. A stacked package comprising:

a first semiconductor package;

a second semiconductor package stacked on the first semiconductor package;

a molding member comprising a plurality of plug holes formed therein, each plug hole comprising a plug that electrically connects the first semiconductor package and the second semiconductor package; and

a plurality of spacers formed on an upper surface of the molding member between the first semiconductor package and the second semiconductor package, each of the spacers having a substantially same height,

wherein the spacers are configured to support the second semiconductor package to permit electrical connection between the first semiconductor package and the second semiconductor package by the plugs and to prevent adjacent plugs from electrically connecting to each other by capillary action, during heating of the stacked package.