Chip structure and process for forming the same

• US 8,546,947 B2
• Filed: 07/26/2011
• Issued: 10/01/2013
• Est. Priority Date: 12/13/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Lin, Mou-Shiung, Huang, Ching-Cheng
• Primary Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US13/191,356
• Publication Number:
  US 20110278727A1
• Time in Patent Office: 798 Days
• Field of Search: 257/759, 257/750, 257/758, 257/762, 257/763
• US Class Current: 257/759
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0558 being stacked
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 27/0248 : for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

Claims

1. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer, and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a first dielectric layer between said first and second copper layers, wherein said copper plug is in said first dielectric layer;

an insulating layer over said silicon substrate, said first dielectric layer and said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening;

a first metal layer on said first contact point and over said insulating layer, wherein said first metal layer comprises a first conductive layer and an aluminum layer on said first conductive layer;

a second dielectric layer over said first metal layer and said insulating layer, wherein a second opening in said second dielectric layer is over a second contact point of said first metal layer; and

a second metal layer over said second contact point and said second dielectric layer, wherein said second metal layer comprises a second conductive layer and a gold-containing layer over said second conductive layer, wherein said second metal layer is connected to said second contact point through said second opening.

2. The chip of claim 1, wherein said first conductive layer comprises titanium.

3. The chip of claim 1, wherein said second dielectric layer comprises a polymer layer.

4. The chip of claim 1, wherein said insulating layer comprises silicon nitride.

5. The chip of claim 1, wherein said insulating layer comprises silicon oxide.

6. The chip of claim 1 further comprising a polymer layer between said first metal layer and said insulating layer.

7. The chip of claim 1, wherein said second metal layer is configured to be connected to an external circuit by a tape-automated-bonding type.

8. The chip of claim 1, wherein said second metal layer is configured to be connected to an external circuit by a flip-chip type.

9. The chip of claim 1, wherein said second metal layer is configured to be connected to an external circuit by a wire-bonding type.

10. The chip of claim 1, wherein said first opening has a width between 0.5 and 20 micrometers.

11. The chip of claim 1, wherein said second conductive layer further comprises a titanium-containing layer.

12. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer, and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a first dielectric layer between said first and second copper layers, wherein said copper plug is in said first dielectric layer;

an insulating layer over said silicon substrate, said first dielectric layer and said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening;

a first metal layer on said first contact point and over said insulating layer, wherein said first metal layer comprises a first conductive layer and an aluminum layer on said first conductive layer;

a second dielectric layer over said first metal layer and said insulating layer, wherein a second opening in said second dielectric layer is over a second contact point of said first metal layer; and

a second metal layer over said second contact point and said second dielectric layer, wherein said second metal layer comprises a second conductive layer and a third copper layer over said second conductive layer, wherein said second metal layer is connected to said second contact point through said second opening.

13. The chip of claim 12, wherein said first conductive layer comprises titanium.

14. The chip of claim 12, wherein said second dielectric layer comprises a polymer layer.

15. The chip of claim 12, wherein said insulating layer comprises silicon nitride.

16. The chip of claim 12, wherein said insulating layer comprises silicon oxide.

17. The chip of claim 12 further comprising a polymer layer between said first metal layer and said insulating layer.

18. The chip of claim 12, wherein said second metal layer is configured to be connected to an external circuit by a tape-automated-bonding type.

19. The chip of claim 12, wherein said second metal layer is configured to be connected to an external circuit by a flip-chip type.

20. The chip of claim 12, wherein said second metal layer is configured to be connected to an external circuit by a wire-bonding type.

21. The chip of claim 12, wherein said first opening has a width between 0.5 and 20 micrometers.

22. The chip of claim 12, wherein said second conductive layer comprises a titanium-containing layer.

23. A chip comprising:

a silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first copper layer, a second copper layer over said first copper layer, and a copper plug between said first and second copper layers, wherein said second copper layer is connected to said first copper layer through said copper plug;

a first dielectric layer between said first and second copper layers, wherein said copper plug is in said first dielectric layer;

an insulating layer over said silicon substrate, said first dielectric layer and said metallization structure, wherein a first opening in said insulating layer is over a first contact point of said metallization structure, and said first contact point is at a bottom of said first opening, and wherein a second opening in said insulating layer is over a second contact point of said metallization structure, and said second contact point is at a bottom of said second opening;

a metal interconnect on said first and second contact points and over said insulating layer, wherein said first contact point is connected to said second contact point through said metal interconnect, wherein said metal interconnect comprises a conductive layer and an aluminum layer on said conductive layer; and

a second dielectric layer over said metal interconnect, wherein no opening in said second dielectric layer is vertically over said metal interconnect.

24. The chip of claim 23, wherein said conductive layer comprises titanium.

25. The chip of claim 23, wherein said second dielectric layer comprises a polymer layer.

26. The chip of claim 23 further comprising a polymer layer between said metal interconnect and said insulating layer.

27. The chip of claim 23, wherein said insulating layer comprises silicon nitride.

28. The chip of claim 23, wherein said insulating layer comprises silicon oxide.

29. The chip of claim 23, wherein said first opening has a width between 0.5 and 20 micrometers.

30. The chip of claim 23, wherein said first contact point is provided by a first conductive pad of said metallization structure, and said second contact point is provided by a second conductive pad of said metallization structure, wherein said first conductive pad has a portion spaced apart from said second conductive pad.