Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit

• US 8,546,953 B2
• Filed: 12/13/2011
• Issued: 10/01/2013
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Horng, Jaw-Juinn, Yu, Chia-Lin, Chen, Chung-Hui, Yeh, Der-Chyang, Peng, Yung-Chow
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US13/324,405
• Publication Number:
  US 20130147057A1
• Time in Patent Office: 658 Days
• Field of Search: 257/276, 257/341, 257/401, 257/621, 257/698, 257/774, 257/E23.067, 438/667
• US Class Current: 257/774
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to V_DD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Claims

1. A semiconductor device comprising:

an active semiconductor device formed on a surface of a semiconductor substrate;

an isolation through silicon via (TSV) extending through said semiconductor substrate and laterally spaced from said active semiconductor device and next to a surface dopant impurity region of a first dopant impurity type disposed in said surface between said isolation TSV and said active semiconductor device, said surface dopant impurity region having a dopant concentration different from said substrate; and

said isolation TSV surrounded laterally by a surrounding dopant impurity region that forms sidewalls of said isolation TSV, said surrounding dopant impurity region being one of a P-type dopant impurity region coupled to ground and an N-type dopant impurity region coupled to V_DD.

2. The semiconductor device as in claim 1, wherein said isolation TSV further includes an oxide liner formed on said sidewalls, said surrounding dopant impurity region surrounds said oxide liner and each of said surrounding dopant impurity region and said oxide liner extend from said surface to a bottom surface of said semiconductor substrate.

3. The semiconductor device as in claim 1, further comprising an active TSV containing a conductive line carrying a signal and extending through said semiconductor substrate, said isolation TSV interposed between said active TSV and said active semiconductor device and wherein said active semiconductor device comprises a transistor.

4. The semiconductor device as in claim 3, further comprising a plurality of further isolation TSVs forming an array, said active TSV surrounded by said array and isolated from said transistor by said array.

5. The semiconductor device as in claim 3, wherein said active TSV includes an oxide liner formed on sidewalls thereof and a surrounding dopant impurity region that laterally surrounds said oxide liner.

6. The semiconductor device as in claim 1, wherein said first dopant impurity type comprises P-type, said surrounding dopant impurity region comprises said P-type dopant impurity region coupled to ground and overlaps with said surface dopant impurity region of said first dopant impurity type, and said isolation TSV contains a copper lead therein.

7. The semiconductor device as in claim 1, wherein said first dopant impurity type comprises N-type and said surrounding dopant impurity region comprises said N-type dopant impurity region coupled to V_DD.

8. The semiconductor device as in claim 7, wherein said surrounding dopant impurity region overlaps with said surface dopant impurity region of said first dopant impurity type, said semiconductor substrate comprises a P-type material, said isolation TSV is coupled to V_DD through said surface dopant impurity which is coupled to V_DD, and said isolation TSV contains a copper lead therein.

9. The semiconductor device as in claim 1, wherein said surrounding dopant impurity region extends from said surface to a termination location above a bottom surface of said semiconductor substrate.

10. The semiconductor device as in claim 1, wherein said isolation TSV is a P-type isolation TSV with said surrounding dopant impurity region comprising said P-type dopant impurity region coupled to ground and said first dopant impurity type comprising P-type and further comprising:

a plurality of further of said P-type isolation TSVs and a plurality of N-type isolation TSVs, each said N-type isolation TSV having said surrounding dopant impurity region being an N-type dopant impurity region disposed next to a further N-type dopant impurity region and coupled to V_DD;

an active TSV structure containing a conductive lead, carrying a signal and extending through said substrate, and

wherein said active TSV structure is surrounded by an array of said N-type isolation TSVs and said array of N-type isolation TSVs is surrounded by an array of said P-type isolation TSVs.

11. A method for forming a semiconductor device, said method comprising:

providing a semiconductor substrate with a surface having an active semiconductor device disposed thereon and a surface dopant impurity region of a first dopant impurity type disposed therein, said surface dopant impurity region having a dopant concentration different from said substrate;

forming a through silicon via (TSV) opening next to said surface dopant impurity region and extending downwardly from said surface and into said semiconductor substrate, said surface dopant impurity region disposed between said TSV opening and said active semiconductor device;

forming a surrounding dopant impurity region surrounding said TSV opening, said surrounding dopant impurity region being one of a P-type dopant impurity region and an N-type dopant impurity region; and

electrically coupling said surrounding dopant impurity region by one of coupling said P-type dopant impurity region to ground when said surrounding dopant impurity comprises a P-type dopant impurity region, and coupling said N-type dopant impurity region to V_DD when said surrounding dopant impurity comprises an N-type dopant impurity region.

12. The method as in claim 11, further comprising thermally oxidizing sidewalls of said TSV opening after said forming a surrounding dopant impurity region.

13. The method as in claim 12, wherein

said first dopant impurity type comprises P-type,

said surrounding dopant impurity region comprises said P-type dopant impurity region and overlaps said surface dopant impurity region of said first dopant impurity type,

said semiconductor substrate comprises a P-type substrate, and

said electrically coupling comprises filling said TSV isolation structure with a conductive material and coupling said TSV isolation structure to ground through said surface dopant impurity region.

14. The method as in claim 12, wherein

said first dopant impurity type comprises N-type,

said surrounding dopant impurity region comprises said N-type dopant impurity region and overlaps said surface dopant impurity region,

said semiconductor substrate comprises a P-type substrate, and

said electrically coupling comprises filling said TSV isolation structure with a conductive material and coupling said TSV isolation structure to V_DD through said surface dopant impurity region.

15. The method as in claim 11, wherein said forming a surrounding dopant impurity region comprises angled ion implantation, and further comprising oxidizing sidewalls of said TSV opening to form an oxide liner thereon, after said angled ion implantation.

16. The method as in claim 11, wherein said forming a surrounding dopant impurity region comprises in-situ plasma doping and further comprising backgrinding an opposed backside surface of said semiconductor substrate such that said TSV opening extends completely through said substrate.

17. A method for forming a semiconductor device, said method comprising:

providing a semiconductor substrate with a surface having an active semiconductor device disposed thereon;

forming a plurality of through silicon vias (TSV) extending through said semiconductor substrate, said plurality of TSVs including an active TSV including a conductive structure carrying an electrical signal therein, an array of first TSV isolation structures surrounded by corresponding first surrounding dopant impurity regions and an array of second TSV isolation structures surrounded by corresponding second surrounding dopant impurity regions; and

wherein said active TSV is separated from said active semiconductor device by at least some of said first TSV isolation structures and said second TSV isolation structures.

18. The method as in claim 17, wherein:

said first TSV isolation structures comprise a first one of N-type and P-type TSV isolation structures and said first surrounding dopant impurity regions comprise said first one of N-type and P-type surrounding dopant impurity regions;

said second TSV isolation structures comprise the other of N-type and P-type TSV isolation structures said second surrounding dopant impurity regions comprise said other of N-type and P-type surrounding dopant impurity regions; and

further comprising coupling said N-type TSV isolation structures to V_DD and coupling said P-type TSV isolation structures to ground.

19. The method as in claim 18, further comprising forming N-type surface dopant impurity regions adjacent and overlapping said N-type surrounding dopant impurity regions and forming P-type surface dopant impurity regions adjacent and overlapping said P-type surrounding dopant impurity regions, and

wherein said coupling said N-type TSV isolation structures comprises coupling said N-type surface dopant impurity regions to V_DD and wherein said coupling said P-type TSV isolation structures comprises coupling said P-type surface dopant impurity regions to ground.

20. The method as in claim 17, wherein said forming a plurality of TSVs includes said active TSV surrounded by a corresponding active TSV surrounding dopant impurity region and etching to form via openings extending into said substrate and forming said corresponding first, second and active TSV surrounding dopant impurity regions using angled ion implantation, and further includes oxidizing sidewalls of said TSVs to form respective oxide liners, wherein said corresponding first, second and active TSV surrounding dopant impurity regions surround said respective oxide liners, and said first and second TSV isolation structures each comprise N-type or P-type isolation structures.