Phase-locked loops that share a loop filter

• US 8,547,151 B2
• Filed: 02/28/2012
• Issued: 10/01/2013
• Est. Priority Date: 11/30/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Kuo, Feng Wei, Chi, Shyh-An, Chen, Huan-Neng, Chen, Yen-Jen, Jou, Chewn-Pu
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US13/407,394
• Publication Number:
  US 20130135018A1
• Time in Patent Office: 581 Days
• Field of Search: None
• US Class Current: 327/156
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.

Claims

1. An integrated circuit die stack, comprising:

a first and a second die connected to each other, each of the first and second dies comprising at least one phase-locked loop (PLL),

wherein PLLs in the first and second dies share a common loop filter to form corresponding feedback loops.

2. The integrated circuit die stack of claim 1, wherein the loop filter comprises a plurality of programmable connection elements, and wherein the plurality of programmable connection elements are configured to activate one of the corresponding feedback loops at a time.

3. The integrated circuit die stack of claim 1, wherein the loop filter is configured to provide similar bandwidth to the corresponding feedback loops.

4. The integrated circuit die stack of claim 1, wherein the loop filter is configured to provide configurable bandwidths to the corresponding feedback loops.

5. The integrated circuit die stack of claim 1, wherein each PLL in the first and second dies comprises a phase frequency detector, a charge pump, a voltage controlled oscillator and a divider.

6. The integrated circuit die stack of claim 1, wherein the loop filter comprises a plurality of capacitors, and wherein the pluralities of capacitors are formed by Metal-Insulator-Metal (MIM) capacitors and/or Metal-Oxide-Metal (MOM) capacitors.

7. The integrated circuit die stack of claim 1, further comprising an interposer that the first and second dies are stacked on, and wherein the common loop filter is located in the interposer.

8. An integrated circuit die stack, comprising:

a first die comprising at least one voltage controlled oscillator and divider;

a second die comprising at least another voltage controlled oscillator and divider;

a shared phase frequency detector;

a shared charge pump; and

a shared loop filter,

wherein

the first and second dies are electrically connected to each other;

the at least one voltage controlled oscillator and the divider in the first die combine with the shared phase frequency detector, the shared charge pump, and the shared loop filter to form a PLL feedback loop; and

the at least another voltage controlled oscillator and the divider in the second die combines with the shared phase frequency detector, the shared charge pump, and the shared loop filter to form another PLL feedback loop.

9. The integrated circuit die stack of claim 8, wherein the shared loop filter comprises a plurality of programmable connection elements, and wherein the plurality of programmable connection elements are configured to activate one of the PLL feedback loops at a time.

10. The integrated circuit die stack of claim 8, wherein the shared loop filter is configured to provide similar bandwidths to the corresponding feedback loops.

11. The integrated circuit die stack of claim 8, wherein the shared loop filter is configured to provide configurable bandwidths to the corresponding feedback loops.

12. The integrated circuit die stack of claim 8, wherein periodic phase locking for each of the feedback loops is performed continuously during functional operations of the integrated circuit die stack.

13. The integrated circuit die stack of claim 8, wherein the shared loop filter comprises a plurality of capacitors, and wherein the pluralities of capacitors are formed by Metal-Insulator-Metal (MIM) capacitors and/or Metal-Oxide-Metal (MOM) capacitors.

14. The integrated circuit die stack of claim 8, further comprising an interposer that the first and second dies are stacked on;

and wherein the shared phase frequency detector, the shared charge pump, and the shared loop filter are located in the interposer.

15. An integrated circuit die stack, comprising:

a first die comprises at least one phase-locked loop (PLL);

a second die comprises at least another PLL; and

a shared loop filter with a plurality of programmable connection elements,

wherein

the first and second dies are electrically connected to each other;

elements of the at least one PLL in the first die combine with the shared loop filter to form a PLL feedback loop;

elements of the at least one PLL in the second die combine with the shared loop filter to form another PLL feedback loop; and

the plurality of programmable connection elements are configured to activate one of the PLL feedback loops at a time.

16. The integrated circuit die stack of claim 15, wherein shared the loop filter is configured to provide similar bandwidths to the corresponding feedback loops.

17. The integrated circuit die stack of claim 15, wherein the shared loop filter is configured to provide configurable bandwidths to the corresponding feedback loops.

18. The integrated circuit die stack of claim 15, wherein each of the at least one PLL in the first and second dies comprises a phase frequency detector, a charge pump, a voltage controlled oscillator and a divider.

19. The integrated circuit die stack of claim 15, wherein the shared loop filter comprises a plurality of capacitors, and wherein the pluralities of capacitors are formed by Metal-Insulator-Metal (MIM) capacitors and/or Metal-Oxide-Metal (MOM) capacitors.

20. The integrated circuit die stack of claim 15, further comprising an interposer that the first and second dies are stacked on, wherein the shared loop filter is located in the interposer.