Sampling

• US 8,547,160 B2
• Filed: 12/12/2012
• Issued: 10/01/2013
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Dedic, Ian Juso, Allen, Gavin Lambertus
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): Almo, Khareem E
• Application Number:
  US13/712,522
• Publication Number:
  US 20130147647A1
• Time in Patent Office: 293 Days
• Field of Search: None
• US Class Current: 327/415
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: H01H 9/54 Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere
• CPC Class Codes: H03K 17/00 Electronic switching or gating, i.e. not by contact-making and –breaking gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03M 1/002 Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
• CPC Class Codes: H03M 1/0614 of harmonic distortion H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/0881 by forcing a gradual change from one output level to the next, e.g. soft-start
• CPC Class Codes: H03M 1/1009 Calibration
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/121 Interleaved, i.e. using multiple converters or converter parts for one channel
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/1245 Details of sampling arrangements or methods
• CPC Class Codes: H03M 1/126 Multi-rate systems, i.e. adaptive to different fixed sampling rates

Abstract

There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

Claims

1. Current-mode circuitry for sampling a current signal, the circuitry comprising:

a first node configured to receive the current signal;

a plurality of second nodes conductively connectable to the first node along respective paths;

a steering circuit configured to control connections between the first node and the second nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

a reset circuit coupled to one of the second nodes, and configured, during a period between successive packets of charge for the one of the second nodes, to bring a voltage potential of the one of the second nodes to a first value.

2. The current-mode circuitry of claim 1,

wherein the reset circuit is configured to cause the voltage potential of the one of the second nodes to return to the same value between successive packets of charge for the one of the second nodes.

3. The current-mode circuitry of claim 1, comprising a plurality of the reset circuits, each of the plurality of the reset circuits being for a different one of the second nodes.

4. Current-mode circuitry for sampling first and second current signals that are complementary to each other, the circuitry comprising:

first and second circuits that are complementary to each other, the first circuit configured to sample the first current signal, the second circuit configured to sample the second current signal,

wherein each of the first and second circuits includes;

a first node configured to receive the current signal for the one of the first and second circuits concerned;

a plurality of second nodes conductively connectable to the first node along respective paths; and

a steering circuit configured to control connections between the first node and the second nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

wherein the circuitry includes;

a reset circuit coupled to at least one of the second nodes of the first circuit and a complementary node of the second circuit, the complementary node being complementary to the at least one of the second nodes of the first circuit, and configured, during a period between successive packets of charge for a pair of the at least one of the second nodes of the first circuit and the complementary node of the second circuit, to bring a difference in voltage potential between the nodes of the pair to a second value.

5. The current-mode circuitry of claim 4,

wherein the reset circuit is coupled to both of the nodes of the pair.

6. The current-mode circuitry of claim 4,

wherein the reset circuit is configured to connect at least one of the nodes of the pair to a reference potential to bring the difference in potential to the second value.

7. The current-mode circuitry of claim 4,

wherein the reset circuit is configured to bring the nodes of the pair to the same potential as each other.

8. The current-mode circuitry of claim 7, wherein the reset circuit is coupled between the nodes of the pair, and is configured to couple the nodes of the pair together to bring the nodes of the pair to the same potential as each other.

9. The current-mode circuitry of claim 4, wherein the reset circuit is configured to cause a voltage potential of at least one of the nodes of the pair to return to the same value between successive packets of charge for the nodes of the pair.

10. The current-mode circuitry of claim 4, comprising a plurality of the reset circuits, each of the plurality of the reset circuits being for a different pair of nodes.

11. The current-mode circuitry of claim 4, wherein each of the first and second circuits includes:

a generating circuit configured to generate a sample value for, and on the basis of a characteristic of, each of the packets of charge passing through the second nodes of the one of the first and second circuits concerned, each sample value being indicative of a value of the current signal corresponding to its packet of charge.

12. Current-mode circuitry for sampling first and second current signals that are complementary to each other, the circuitry comprising:

first and second circuits that are complementary to each other, the first circuit configured to sample the first current signal, the second circuit configured to sample the second current signal,

wherein each of the first and second circuits includes;

a root node configured to receive the current signal for the one of the first and second circuits concerned;

a plurality of first-tier nodes conductively connectable directly to the root node;

a plurality of subsequent-tier nodes for each of the first-tier nodes, each of the subsequent-tier nodes being conductively connectable indirectly to the root node along a respective path via the corresponding first-tier node; and

a steering circuit configured to control connections between the root node and the subsequent-tier nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

a reset circuit coupled to at least one of the first and subsequent-tier nodes of the first circuit and a complementary node of the second circuit, the complementary node being complementary to the at least one of the first and subsequent-tier nodes of the first circuit, and configured, during a period between successive packets of charge for a pair of the at least one of the first and subsequent-tier nodes of the first circuit and a complementary node of the second circuit, to bring a difference in voltage potential between the nodes of the pair to a third value.

13. The current-mode circuitry of claim 12,

wherein the reset circuit is coupled to both of the nodes of the pair.

14. The current-mode circuitry of claim 12,

wherein the reset circuit is configured to connect at least one of the nodes of the pair to a reference potential so as to bring the difference in potential to the third value.

15. The current-mode circuitry of claim 12

wherein the reset circuit is configured to bring the nodes of the pair to the same potential as each other.

16. The current-mode circuitry of claim 15,

wherein the reset circuit is coupled between the nodes of the pair, and is configured to couple the nodes of the pair together so as to bring the nodes of the pair to the same potential as each other.

17. The current-mode circuitry of claim 12,

wherein the reset circuit is configured to cause a voltage potential of at least one of the nodes of the pair to return to the same value between successive packets of charge for the nodes of the pair.

18. The current-mode circuitry of claim 12, comprising a plurality of the reset circuits, each of the plurality of the reset circuits being for different pair of nodes.

19. The current-mode circuitry of claim 12,

wherein each of the first and second circuits includes:

a generating circuit configured to generate a sample value for, and on the basis of a characteristic of, each of the packets of charge passing through the subsequent-tier nodes, each sample value being indicative of a value of the current signal corresponding to its packet of charge.

20. Analogue-to-digital conversion circuitry, comprising the current-mode circuitry according to claim 12.

21. Integrated circuitry, comprising the current-mode circuitry according to claim 12.

22. A method of sampling a current signal in current-mode circuitry, the circuitry having a first node configured to receive the current signal and a plurality of second nodes conductively connectable to the first node along respective paths, the method comprising:

controlling such connections between the first node and the second nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

bringing, during a period between successive packets of charge for one of the second nodes, a voltage potential of the one of the second nodes to a fourth value.

23. A method of sampling first and second current signals that are complementary to each other in current-mode circuitry, the circuitry having first and second circuits that are complementary to each other, the first circuit configured to sample the first current signal, the second circuit configured to sample the second current signal,

wherein each of the first and second circuits includes a first node configured to receive the current signal for the one of the first and second circuits concerned and a plurality of second nodes conductively connectable to the first node along respective paths,

the method comprising:

for each of the first and second circuits, controlling connections between the first node and the second nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

for at least one of the second nodes of the first circuit and a complementary node of the second circuit, the complementary node being complementary to the at least one of the second nodes of the first circuit, during a period between successive packets of charge for a pair of the at least one of the second nodes of the first circuit and the complementary node of the second circuit, bringing a difference in voltage potential between the nodes of the pair to a fifth value.

24. A method of sampling first and second current signals that are complementary to each other in current-mode circuitry, the circuitry having first and second circuits that are complementary to each other, the first circuit configured to sample the first current signal, the second circuit configured to sample the second current signal,

wherein each of the first and second circuits includes a root node configured to receive the current signal for the one of the first and second circuits concerned, a plurality of first-tier nodes conductively connectable directly to the root node, and a plurality of subsequent-tier nodes for each of the first-tier nodes, each of the plurality of subsequent-tier nodes being conductively connectable indirectly to the root node along a respective path via the corresponding first-tier node, the method comprising:

for each of the first and second circuits, controlling connections between the root node and the subsequent-tier nodes so that different packets of charge making up the current signal are steered along different ones of the paths over time; and

for at least one of the first and subsequent-tier nodes of the first circuit and a complementary node of the second circuit, the complementary node being complementary to the at least one of the first and subsequent-tier nodes of the first circuit, during a period between successive packets of charge for a pair of the at least one of the first and subsequent-tier nodes of the first circuit and the complementary node of the second circuit, bringing a difference in voltage potential between the nodes of the pair to a sixth value.