Active matrix substrate, liquid crystal panel, liquid crystal display device, liquid crystal display unit and television receiver

• US 8,547,492 B2
• Filed: 10/22/2009
• Issued: 10/01/2013
• Est. Priority Date: 02/03/2009
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tsubata, Toshihide
• Primary Examiner(s): CHIEN, LUCY P
• Application Number:
  US13/146,637
• Publication Number:
  US 20110279735A1
• Time in Patent Office: 1,440 Days
• Field of Search: None
• US Class Current: 349/39
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G02F 1/134354 the sub-pixels being capacitively coupled
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode

Abstract

Provided is an active matrix substrate including a capacitance electrode (47a) electrically connected to a pixel electrode (17a), in which a storage capacitance wiring (18p) is formed in the layer between the capacitance electrode (47a) and the pixel electrode (17a), the capacitance electrode (47a) and the storage capacitance wiring (18p) overlap through a first insulating film and the storage capacitance wiring (18p) and the pixel electrode (17a) overlap through a second insulating film. With this configuration, in the active matrix substrate, the storage capacitance value can be increased without lowering the aperture ratio.

Claims

1. An active matrix substrate, comprising:

scan signal lines extending in a row direction when data signal lines extend in a column direction, a transistor connected to said data signal line and the scan signal line; and

a storage capacitance wiring,

wherein, in a single pixel region, a first pixel electrode connected to said data signal line through the transistor is provided,

wherein, in the single pixel region, a first capacitance electrode electrically connected to said first pixel electrode is provided,

wherein said storage capacitance wiring is formed in a layer between said first capacitance electrode and said first pixel electrode,

wherein said first capacitance electrode and said storage capacitance wiring overlap through a first insulating film, and said storage capacitance wiring and said first pixel electrode overlap through a second insulating film, and

wherein said first insulating film is a gate insulating film.

2. The active matrix substrate according to claim 1, wherein said first capacitance electrode is formed in a same layer with said scan signal line.

3. The active matrix substrate according to claim 1, wherein said storage capacitance wiring is formed in a same layer with said data signal line.

4. The active matrix substrate according to claim 1, wherein said storage capacitance wiring extends in the column direction.

5. The active matrix substrate according to claim 1, wherein the thickness of said second insulating film is equal to or smaller than the thickness of said first insulating film.

6. The active matrix substrate according to claim 1,

wherein said second insulating film is configured to include at least an interlayer insulating film.

7. The active matrix substrate according to claim 1, wherein said second insulating film is an interlayer insulating film that covers a channel of said transistor.

8. The active matrix substrate according to claim 1, wherein said first capacitance electrode has a row direction width that is wider than a row direction width of the storage capacitance wiring when observed in a plan view.

9. The active matrix substrate according to claim 1,

wherein neighboring pixel regions have different liquid crystal thicknesses, and

wherein neighboring pixel regions have different overlapping areas of the first capacitance electrode and the storage capacitance wiring in accordance with the thicknesses of a liquid crystal layer.

10. The active matrix substrate according to claim 1, wherein a capacitance lead-out electrode led out from said first capacitance electrode partially overlaps said data signal line through said first insulating film.

11. The active matrix substrate according to claim 1, further comprising a second pixel electrode connected to said first pixel electrode through a capacitance.

12. The active matrix substrate according to claim 11, further comprising a second capacitance electrode electrically connected to said first pixel electrode,

wherein said capacitance is formed between the second capacitance electrode and the second pixel electrode due to an overlapping of the second capacitance electrode and the second pixel electrode through the second insulating film.

13. The active matrix substrate according to claim 11, further comprising a second capacitance electrode electrically connected to said first capacitance electrode,

wherein said capacitance is formed between said second capacitance electrode and said second pixel electrode due to an overlapping of said second capacitance electrode and said second pixel electrode through said first and second insulating films.

14. The active matrix substrate according to claim 11, wherein said first and second pixel electrodes are arranged in the column direction.

15. The active matrix substrate according to claim 11, wherein said first and second pixel electrodes are arranged in the row direction.

16. The active matrix substrate according to claim 15, wherein in one of two pixel regions arranged next to each other in the column direction, said transistor is connected to one of two adjacent data signal lines, and in the other of said two pixel regions, said transistor is connected to the other of said two data signal lines.

17. The active matrix substrate according to claim 16, wherein said first pixel electrode provided in one of said two pixel regions and said second pixel electrode provided in the other pixel region are adjacent to each other in the column direction.

18. The active matrix substrate according to claim 15, wherein said storage capacitance wiring extends in the column direction and overlaps with said first and second pixel electrodes and a space between them.

19. The active matrix substrate according to claim 18, further comprising a third capacitance electrode formed in a same layer with said first capacitance electrode and said scan signal line,

wherein said first capacitance electrode connected to said first pixel electrode through a contact hole reaches under said second pixel electrode, crossing under said storage capacitance wiring;

and said third capacitance electrode connected to said second pixel electrode through a contact hole reaches under said first pixel electrode, crossing under said storage capacitance wiring.

20. The active matrix substrate according to claim 19, wherein said first and third capacitance electrodes are arranged symmetrically with respect to a point or a line.

21. The active matrix substrate according to claim 1, wherein said first capacitance electrode is made of a transparent electrode layer.

22. The active matrix substrate according to claim 1, wherein said first pixel electrode and said first capacitance electrode are connected together through a contact hole that runs through said first and second insulating films.

23. The active matrix substrate according to claim 1, wherein a drain lead-out electrode led out from one of conductive electrodes of said transistor and said first pixel electrode are inter-connected through a contact hole, and said first pixel electrode and said first capacitance electrode are connected together through a contact hole which is different from said contact hole.

24. The active matrix substrate according to claim 1, wherein said first capacitance electrode, a drain lead-out electrode led out from one of conductive electrodes of said transistor, and said first pixel electrode are inter-connected through a same contact hole running through said first and second insulating films.

25. The active matrix substrate according to claim 24, wherein an opening portion of said contact hole is formed in said drain lead-out electrode, and said drain lead-out electrode is removed or notched at a location that overlaps said first capacitance electrode.

26. A liquid crystal panel comprising the active matrix substrate according to claim 1.

27. A liquid crystal display unit comprising the liquid crystal panel according to claim 26 and drivers.

28. A liquid crystal display device comprising the liquid crystal display unit according to claim 27 and a light source device.

29. A television receiver comprising the liquid crystal display device according to claim 28 and a tuner unit receiving television broadcasting.