Stacked memory device and method thereof
First Claim
Patent Images
1. A stacked memory device comprising:
- a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells;
a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information; and
at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit, wherein the at least one second active circuit unit includes a plurality of main decoders, each of the at least one second active circuit interposed between at least two of the memory layers, and wherein the first active circuit unit, the at least one second active circuit unit, and the memory layers are in separate layers from each other.
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Abstract
A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.
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Citations
23 Claims
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1. A stacked memory device comprising:
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a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells; a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information; and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit, wherein the at least one second active circuit unit includes a plurality of main decoders, each of the at least one second active circuit interposed between at least two of the memory layers, and wherein the first active circuit unit, the at least one second active circuit unit, and the memory layers are in separate layers from each other. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A stacked memory device comprising:
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a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells; a first active circuit unit including a level decoder and a pre-decoder, where the level decoder is configured to decode vertical address information of at least one of the memory cells to generate a level selection signal, and the pre-decoder is configured to decode horizontal address information of at least one of the memory cells to generate a row/column signal; and a plurality of second active circuit units stacked on the first active circuit unit in order to classify and manage the plurality of memory layers according to a plurality of groups of memory layers, wherein each of the second active circuit units includes a main decoder configured to decode the level selection signal and the row/column selection signal to generate a memory selection signal. - View Dependent Claims (19)
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20. A method of accessing a stacked memory device, comprising:
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providing a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells; classifying and processing address information at a first active circuit unit for at least one of the memory cells as vertical address information and horizontal address information; and generating a memory selection signal from at least one second active circuit unit for at least one of the memory cells based on signals processed by the classifying and processing, wherein the at least one second active circuit unit includes a plurality of main decoders, each of the at least one second active circuit interposed between at least two of the memory layers, and wherein the first active circuit unit, the at least one second active circuit unit, and the memory layers are in separate layers from each other. - View Dependent Claims (21, 22, 23)
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Specification