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Semiconductor memory device having an electrically floating body transistor

  • US 8,547,756 B2
  • Filed: 10/04/2010
  • Issued: 10/01/2013
  • Est. Priority Date: 10/04/2010
  • Status: Active Grant
First Claim
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1. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:

  • applying an electrical signal to buried regions of said memory cells,wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;

    wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type; and

    wherein said electrical signal to said buried regions are of different amplitude or polarity, depending on an operation performed on said memory cell.

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