Semiconductor memory device having an electrically floating body transistor
First Claim
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1. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:
- applying an electrical signal to buried regions of said memory cells,wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type;
wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type; and
wherein said electrical signal to said buried regions are of different amplitude or polarity, depending on an operation performed on said memory cell.
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Abstract
A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
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Citations
34 Claims
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1. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:
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applying an electrical signal to buried regions of said memory cells, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type; and wherein said electrical signal to said buried regions are of different amplitude or polarity, depending on an operation performed on said memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:
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applying electrical signals to a buried region of a memory cell of said semiconductor memory array; and causing a current to flow solely into said buried region, wherein the memory cell comprises; a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; the buried region located beneath the surface of the memory cell, the buried region having a second conductivity type; and a third region defining at least a further portion of the surface of the memory cell, the third region having the second conductivity type. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method of operating a semiconductor memory array having rows and columns of memory cells, the method comprising:
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applying electrical signals to a memory cell of the semiconductor memory array having at least one surface, wherein the memory cell comprises; a floating body region having a first conductivity type, wherein a surface of the semiconductor memory array defines at least a portion of the floating body region; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type; and a third region defining at least a further portion of the surface of the memory cell, said third region having the second conductivity type; and causing a current to flow solely from the third region of said memory cell to the buried region of said memory cell. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of operating a semiconductor memory array having rows and columns of multi-level memory cells with a surface, the method comprising:
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applying electrical signals characterized by at least three amplitude or polarity values to a buried region of a memory cell of the semiconductor memory array, wherein the memory cell comprises; a floating body region defining at least a portion of the surface, the floating body region having a first conductivity type; the buried region, wherein the buried region is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type; and a third region defining at least a further portion of the surface, the third region having the second conductivity type. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification