Dynamic memory and I/O management in a GPS receiver
First Claim
1. A Global Positioning System (GPS) receiver, comprising:
- a Radio Frequency (RF) portion; and
a baseband portion, coupled to the RF portion;
wherein the baseband portion comprises a memory and a memory controller, the memory configured as a plurality of buses, wherein the buses have at least two different bit widths, the memory comprising a fixed plurality of blocks wherein the blocks are dynamically allocated between an instruction memory block and a data memory block; and
wherein the baseband portion further comprises a programmable drive controller configured to change a drive current of a data signal within the baseband portion of the GPS receiver based on a condition of the GPS receiver, wherein the drive current is selected from a group consisting of at least a first drive current and a second drive current, each of which are different and not zero.
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Accused Products
Abstract
Clock compensation for GPS receivers. A receiver in accordance with the present invention comprises a Radio Frequency (RF) portion, and a baseband portion, coupled to the RF portion, wherein the baseband portion comprises a crystal, an oscillator, coupled to the crystal, wherein the oscillator generates a clock signal based on a signal received from the crystal, a counter, coupled to the oscillator via the clock signal, a comparator, coupled to the counter, a controller, at least one logic gate, coupled to the comparator and the controller, and a combiner, coupled to the at least one logic gate, the controller, and the counter and producing an accurate clock signal therefrom.
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Citations
10 Claims
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1. A Global Positioning System (GPS) receiver, comprising:
- a Radio Frequency (RF) portion; and
a baseband portion, coupled to the RF portion;wherein the baseband portion comprises a memory and a memory controller, the memory configured as a plurality of buses, wherein the buses have at least two different bit widths, the memory comprising a fixed plurality of blocks wherein the blocks are dynamically allocated between an instruction memory block and a data memory block; and wherein the baseband portion further comprises a programmable drive controller configured to change a drive current of a data signal within the baseband portion of the GPS receiver based on a condition of the GPS receiver, wherein the drive current is selected from a group consisting of at least a first drive current and a second drive current, each of which are different and not zero. - View Dependent Claims (2, 3, 4, 5)
- a Radio Frequency (RF) portion; and
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6. A Global Positioning System (GPS) receiver, comprising:
- a Radio Frequency (RF) portion; and
a baseband portion, coupled to the RF portion, the baseband portion comprising a programmable drive controller, wherein the programmable drive controller changes a drive current of a data signal within the baseband portion of the GPS receiver based on a condition of the GPS receiver, wherein the drive current is selected from a group consisting of at least a first drive current and a second drive current, each of which are different and not zero; andwherein the baseband portion further comprises a memory and a memory controller, the memory configured as a plurality of buses, wherein the buses have at least two different bit widths, the memory comprising a fixed plurality of blocks wherein the blocks are dynamically allocated between an instruction memory block and a data memory block. - View Dependent Claims (7, 8, 9, 10)
- a Radio Frequency (RF) portion; and
Specification