Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry

• US 8,549,055 B2
• Filed: 03/03/2010
• Issued: 10/01/2013
• Est. Priority Date: 03/03/2009
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Streicher, Keone, Langhammer, Martin, Lin, Yi-Wen, Leung, Wai-Bor, Lewis, David, Mauer, Volker, Lui, Henry Y., Demirsoy, Suleyman Sirri, Yi, Hyun
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US12/716,878
• Publication Number:
  US 20100228806A1
• Time in Patent Office: 1,308 Days
• Field of Search: None
• US Class Current: 708/230
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/06 Systolic
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Claims

1. Circuitry that is usable to perform a selectable one of (1) one M-bit by M-bit (“

M×

M”

) multiplication and (2) two N-bit by N-bit (“

N×

N”

) multiplications, where M is equal to 1.5N, comprising;

N×

N multiplier circuitry;

0.5N×

M multiplier circuitry;

0.5N×

N multiplier circuitry;

first circuitry for additively combining outputs of the 0.5N×

M multiplier circuitry and outputs of the 0.5N×

N multiplier circuitry;

shifter circuitry for shifting outputs of the N×

N multiplier circuitry by a selectable one of (1) zero bits positions and (2) N bit positions toward greater arithmetic significance; and

second circuitry for additively combining outputs of the shifter circuitry and outputs of the first circuitry.

2. The circuitry defined in claim 1 where N is equal to 18 and M is equal to 27.

3. The circuitry defined in claim 1 further comprising:

first, second, third, and fourth pluralities of data signal input leads; and

routing circuitry for controllably routing signals from each of the pluralities to selectable ones of inputs to the multiplier circuitries.

4. The circuitry defined in claim 3 wherein each of the pluralities consists of N data signal input leads.

5. The circuitry defined in claim 4 wherein the routing circuitry comprises:

first, second, third, and fourth N-bit multiplexers, each of which is controllable to route N bits from any one of the pluralities to a respective one of (1) multiplicand inputs to the N×

N multiplier circuitry, (2) multiplier inputs to the N×

N multiplier circuitry;

(3) N less significant multiplicand inputs to the 0.5N×

M multiplier circuitry, and (4) multiplicand inputs to the 0.5N×

N multiplier circuitry; and

first, second, and third 0.5N-bit multiplexers, each of which is controllable to route 0.5N bits from any of at least some of the pluralities to a respective one of (1) 0.5N more significant multiplicand inputs to the 0.5N×

M multiplier circuitry, (2) multiplier inputs to the 0.5N×

M multiplier circuitry, and (3) multiplier inputs to the 0.5N×

N multiplier circuitry.

6. A digital signal processing (“

DSP”

) circuit block comprising;

first means for performing a first N-bit by N-bit (“

N×

N”

) multiplication;

second means for performing a selectable one of (1) a second N×

N multiplication and (2) a 0.5N-bit by M-bit (“

0.5N×

M”

) multiplication and a 0.5N-bit by N-bit (“

0.5N×

N”

) multiplication, where M is equal to 1.5N;

third means for shifting outputs of the first means by a selectable one of (1) zero bit positions and (2) N bit positions toward greater arithmetic significance;

fourth means for additively combining outputs of the second and third means;

fifth means for routing outputs of the fourth means to a first other DSP circuit block; and

sixth means for additively combining outputs of the fourth means and outputs received from a second other DSP circuit block.

7. The DSP circuit block defined in claim 6 wherein the second means comprises:

seventh means for performing the 0.5N×

M multiplication;

eighth means for performing the 0.5N×

N multiplication; and

ninth means for additively combining outputs of the seventh and eighth means, with bits of the outputs of the eighth means being increased in arithmetic significance by 0.5N bit positions relative to bits of the outputs of the seventh means.

8. The DSP circuit block defined in claim 7 further comprising:

tenth means for selectively routing the N most significant bits of an M-bit multiplicand data word to multiplicand inputs to the first means;

eleventh means for selectively routing the N most significant bits of an M-bit multiplier data word to multiplier inputs to the first means;

twelfth means for selectively routing the M-bit multiplicand to the multiplicand inputs to the seventh means;

thirteenth means for selectively routing the 0.5N least significant bits of the multiplier data word to multiplier inputs to the seventh means;

fourteenth means for selectively routing the N most significant bits of the multiplier data word to multiplicand inputs to the eighth means; and

fifteenth means for selectively routing the 0.5N least significant bits of the multiplicand data word to the multiplier inputs to the eighth means.

9. The DSP circuit block defined in claim 6 further comprising:

sixteenth means for receiving multiple pluralities of data input signals for use as inputs to the first and second means;

seventeenth means for selectively pre-adding at least some of the data input signals; and

eighteenth means for selectively applying outputs of the seventeenth means to selected inputs to at least one of the first and second means.

10. The DSP circuit block defined in claim 6 further comprising:

nineteenth means for selectively giving inputs to the second means a systolic register delay.

11. The DSP circuit block defined in claim 6 wherein the fifth means comprises:

twentieth means for shifting the outputs of the fourth means by a selectable one of (1) zero bit positions and (2) N bit positions toward lesser arithmetic significance.

12. The DSP circuit block defined in claim 6 wherein the fifth means comprises:

twenty-first means for selectively alternatively routing output signals indicative of outputs of the sixth means to the first other DSP circuit block.

13. The DSP circuit block defined in claim 12 wherein the twenty-first means comprises:

twenty-second means for selectively giving the output signals indicative of outputs of the sixth means a systolic register delay.

14. The DSP circuit block defined in claim 6 wherein the fifth means comprises:

twenty-third means for alternatively routing signals from the second other DSP circuit block to the first other DSP circuit block.

15. The DSP circuit block defined in claim 6 wherein the sixth means comprises:

twenty-fourth means for registering output signals indicative of outputs of the sixth means; and

twenty-fifth means for applying outputs of the twenty-fourth means to inputs to the sixth means.