Method for supporting multiple libraries characterized at different process, voltage and temperature points

• US 8,549,452 B2
• Filed: 05/06/2010
• Issued: 10/01/2013
• Est. Priority Date: 05/06/2010
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Banerji, Revanta, Abbaspour, Soroush, Feldmann, Peter, Gupta, Hemlata
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Lin, Aric
• Application Number:
  US12/774,766
• Publication Number:
  US 20110276933A1
• Time in Patent Office: 1,244 Days
• Field of Search: 716/102, 716/106, 716108-115, 716/136
• US Class Current: 716/111
• CPC Class Codes: G06F 2111/06 Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]

Abstract

A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.

Claims

1. A method of improving a performance of a VLSI chip design by performing a timing, noise, and power analysis using multiple process, voltage, and temperature (PVT) characterized libraries, the method comprising:

a. using a computer, dividing a PVT space of the characterized libraries into a plurality of regions defined by existing PVT points;

b. pre-processing for each of said regions a static portion of an interpolation function dependent on properties of the characterized libraries and storing the static portion of the interpolation function;

c. using the static portion of the interpolation function for different combinations of parameters subjected to predetermined conditions; and

d. computing timing, noise, and power attributes at selected process settings using the stored static portion and attributes from the characterized libraries and results of the different combinations of the parameters.

2. The method as recited in claim 1, wherein the PVT space is divided into triangular regions.

3. The method as recited in claim 1, wherein the PVT space is divided into tetrahedral regions.

4. The method as recited in claim 2, wherein the PVT space is divided into rectangular regions.

5. The method as recited in claim 2, wherein the PVT space is divided into hyper-rectangular regions.

6. The method as recited in claim 1, wherein the pre-processing is performed by linear regression.

7. The method as recited in claim 1, wherein step d) is performed using a linear multiplication.

8. The method as recited in claim 1 wherein the sub-division of space results in a piecewise-linear interpolation providing continuity over all region boundaries.

9. The method as recited in claim 1 further comprising applying pre-processed information during active runs for determining said attributes at predetermined PVT points, when said PVT space is sub-divided.

10. The method as recited in claim 2, wherein a Delaunay triangulation is utilized for dividing the PVT space into triangles.

11. The method as recited in claim 3, wherein the Delaunay tetrahedralization is utilized for dividing the PVT space into tetrahedral regions.

12. The method as recited in claim 1, where said PVT space includes any process and environmental sources of variations.

13. The method as recited in claim 1 wherein the timing attributes include delays, slews, pin capacitance, limits, timing constraints, voltage waveforms and current waveforms.

14. The method as recited in claim 1 wherein the power attributes includes static power, dynamic power and leakage power.

15. The method as recited in claim 1 wherein the noise attribute includes current waveforms, pin capacitance, noise rejection curves, propagated noise, noisy resistance, and quiet resistance.

16. The method as recited in claim 1 wherein the static portion of an interpolation function is dependent on the process, voltage and temperature (PVT) of the characterized libraries at a region periphery.

17. The method as recited in claim 16, wherein input slew (S_in), output capacitive load (C₁), supply voltage setting (V_dd), temperature (T), and process variable setting (P), are inputs to an interpolation function (F), and wherein the interpolation function is divided into a static portion (H_static), and a dynamic portion of the operation (f_dynamic), the interpolation function being determined by equation:

F(P, Vdd, T, S _in, C_l)=F{H_static{P, Vdd, T}, f_dynamic(S_in, C_l)}.

18. The method as recited in claim 17, wherein an instance delay is a function of the input slew (S_in), and the output capacitive load (C₁) determined by equation:

Delay_req(Sin, C_l)=c₁Delay₁(Sin, C_l)+c₂Delay₂(Sin, C_l)+c₃Delay₃(Sin, C_l)+c₄Delay₄(Sin, C_l) wherein [c₁ c₂ c₃ c₄]=[1 V_reqT_reqP_req]H_static^cached

and wherein Delay1 is a delay of a gate for the Sin, and C₁ at P₁V₁T₁;

Delay2 is the delay of the gate for the Sin and C₁ at P₂V₂T₂;

Delay3 is the delay of the gate for the Sin and C₁ at P₃V₃T₃; and

Delay4 is the delay of the gate for the Sin and C1 at P₄V₄T₄, and wherein C₁, C₂, C₃ and C₄ are dependent on PVT and H_static and are independent from dynamic attributes of the libraries.

19. The method as recited in claim 18, wherein interpolated pin-caps for an instance at P_reqV_reqT_req are determined for every instance in the design, the PVT of each instance in the PVT space being located, and then multiplied by pre-computed H_static, and wherein the PVT of the instance at said P_req, V_req, and T_req is determined by equation:

Pincap_req(Sin, C_l)=c₁Pincap ₁ (Sin, C_l)+c₂Pincap ₂(Sin, C_l)+c₃Pincap₃(Sin, C_l)+c₄Pincap₄(Sin, C₁)

wherein Pincap1 is a pin-cap of the gate for the Sin and C₁ at P₁V₁T₁;

pincap2 is the pin-cap of the gate for the Sin and C₁ at P₂V₂T₂;

pincap3 is the pin-cap of the gate for the Sin and C₁ at P₃V₃T₃; and

pincap4 is the pin-cap of the gate for the Sin and C₁ at P₄V₄T₄. Pin-cap at each library can be calculated using conventional multi-linear interpolation.

20. A non-transitory program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps of improving a performance of a VLSI chip design by performing a timing, noise, and power analysis using multiple process, voltage, and temperature (PVT) characterized libraries, the method steps comprising:

a. using a computer, dividing a PVT space of the characterized libraries into a plurality of regions defined by existing PVT points;

b. pre-processing for each of said regions a static portion of an interpolation function dependent on properties of the characterized libraries, and storing the static portion of the interpolation function;

c. using the static portion of the interpolation function for different combinations of parameters subjected to predetermined conditions; and

d. computing timing, noise, and power attributes at selected process settings using the stored static portion and attributes from the characterized libraries and results of the different combinations of the parameters.