Die expansion bus

• US 8,549,463 B2
• Filed: 09/29/2011
• Issued: 10/01/2013
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Sanjive, Agarwala
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US13/249,218
• Publication Number:
  US 20120084483A1
• Time in Patent Office: 733 Days
• Field of Search: 716/110, 716116-119, 716/138, 710/100, 710/300, 710/305, 710/306, 326 37- 38, 326/47
• US Class Current: 716/138
• CPC Class Codes: G06F 13/14 Handling requests for interconnection or transfer
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing memory mapped control registers associated with the bus subsystems of the supplemental portion of the processing system.

Claims

1. A method for updating a processing system design on a first integrated circuit into a at least one updated processor design on respective second integrated circuits, comprising:

arranging an original processing system design in a substrate in accordance with a substantially fixed layout, wherein the original processing system design includes original data resources for processing data and includes bus subsystems having first memory mapped control registers for controlling the data resources of the original processing system design and second memory mapped control registers for controlling data resources not of the original processing system design, the original processing system design further including a die expansion bus coupled to the bus subsystems and adapted to couple to supplemental bus systems of a supplemental processing system;

constructing a first integrated circuit with the original processing system design;

arranging at least one updated processing system design in a substrate including the original processing system design and a supplemental processing system design with a substantially fixed layout, wherein the supplemental processing system design includes supplemental data resources for processing data and includes supplemental bus subsystems having at least one of the second memory mapped control registers for controlling the data resources of the supplemental processing system, the supplemental bus subsystems arranged to couple to the die expansion bus wherein the original processing system design is operable to control the supplemental data resources of the supplemental processing system design by accessing a corresponding secondary memory mapped control registers associated with the supplemental bus subsystems of the supplemental processing system design, and wherein the layout of the supplemental processing system design is generated after the layout of the original processing system design has been substantially fixed; and

constructing at least one second integrated circuit with a corresponding supplemental processing system design.

2. The method of claim 1, wherein the substantially fixed layout of the original processing system design is provided as a standard cell for integrated circuit design.

3. The method of claim 1, wherein the original bus subsystem is a clocking system that provides first memory mapped control registers for selecting clock signals.

4. The method of claim 1, wherein the original bus subsystem is a power management system that provides first memory mapped control registers for applying various levels of system power to selected resources.

5. The method of claim 1, wherein the original bus subsystem is a verification system that provides first memory mapped control registers for providing test stimulus to and reading test results from the selected resources.

6. The method of claim 1, wherein:

said step of arranging the original processing system design further comprising arranging a plurality of die expansion busses around the periphery of the original processing system design, wherein the plurality of die expansion busses are arranged to couple supplemental bus subsystems of a plurality of supplemental processing system designs to the original bus subsystems.

7. The method of claim 6, wherein:

said step of arranging the updated processing system design further comprising arranging the plurality of supplemental processing system designs around the periphery of the original processing system design and adjacent to an associated die expansion bus.

8. The method of claim 1, wherein:

said step of arranging at least one updated processor system design further comprising coupling the supplemental processing system design that is located on a first die of a die stack to the original processing system design that is on a second die of the die stack using through-silicon-vias (TSVs).

9. The method of claim 1, wherein:

said step of arranging at least one updated processor system design further comprising queuing pending events for transferring data across a bus switch fabric of the original processing system design and a bus switch fabric of the supplemental processing system design.

10. The method of claim 1, wherein:

the die expansion bus includes a cross-domain bridge to couple the bus switch fabric of the original portion of the processing system to the bus switch fabric of the supplemental original portion.

11. The method of claim 10, comprising

transferring data asynchronously across the cross-domain bridge.

12. The method of claim 1, comprising generating a clock in the original portion of the processing system, dividing the clock in the die expansion bus, and receiving the divided clock in the supplemental portion of the processing system.

13. A system on chip, comprising:

an original processing system arranged in a substrate in accordance with a substantially fixed layout, wherein the original processing system includes data resources for processing data and includes bus subsystems having first memory mapped control registers for controlling the data resources of the original portion of the processing system and second memory mapped control registers adapted for controlling data resources not of the original processing system;

a die expansion bus arranged in the substrate, the die expansion bus coupled to to the bus subsystems of the original processing system and adapted to couple to supplemental bus systems of a supplemental processing system, and wherein the original processing system is arranged to control data resources of the supplemental processing system by accessing the second memory mapped control registers associated with the supplemental bus subsystems of the supplemental processing system.

14. The system of claim 13, wherein the is operable to connect to a second die of a die stack using through-silicon-vias (TSVs).