Stack packages using reconstituted wafers

• US 8,551,815 B2
• Filed: 08/01/2008
• Issued: 10/08/2013
• Est. Priority Date: 08/03/2007
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Avsian, Osher, Grinman, Andrey, Humpston, Giles, Margalit, Moti
• Primary Examiner(s): NGO, NGAN V
• Application Number:
  US12/671,993
• Publication Number:
  US 20110248410A1
• Time in Patent Office: 1,894 Days
• Field of Search: 257/685, 257/686, 257/723, 257/724, 257/E23.022, 438/109, 438/110, 438/108, 438/111, 438/113
• US Class Current: 438/108
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/00 Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A stacked microelectronic unit is provided which has a top surface and a bottom surface remote from the top surface and a plurality of vertically stacked microelectronic elements therein, including at least one microelectronic element having a front face adjacent to the top surface and a rear face oriented towards the bottom surface. Each of the microelectronic elements has traces extending from contacts at the front face beyond edges of the microelectronic element. A dielectric layer contacts edges of the microelectronic elements and underlies the rear face of the at least one microelectronic element. Leads are connected to the traces extending along the dielectric layer. Unit contacts, exposed at the top surface, are connected to the leads.

Claims

1. A method of fabricating a stacked microelectronic assembly, comprising:

a) forming a first subassembly including a plurality of spaced apart first microelectronic elements, each first microelectronic element having a front face and contacts exposed at the front face, a rear face remote from the front face, first edges extending between the front and rear faces, a first dielectric layer overlying each of the respective first edges, and a plurality of traces extending from the contacts to beyond the first edges of the first microelectronic elements, the rear faces of the first microelectronic elements being joined to a carrier layer;

b) attaching a plurality of spaced apart second microelectronic elements to the first subassembly, each second microelectronic element having a front face and contacts exposed at the front face, a rear face remote from the front face, second edges extending between the front and rear faces, such that the rear faces of the second microelectronic elements overlie and are adjacent to the front faces of respective ones of the first microelectronic elements, wherein a second dielectric layer overlies each of the respective second edges;

c) after the attaching of the plurality of spaced apart second microelectronic elements to the first subassembly, forming a plurality of traces extending from the contacts of the second microelectronic elements to beyond the second edges of the second microelectronic elements; and

d) forming leads in at least one opening extending between confronting first edges of adjacent ones of the first microelectronic elements and between confronting second edges of adjacent ones of the second microelectronic elements, each of the leads being connected to the traces of at least one of the first and at least one of the second microelectronic elements, and each of the leads formed on and extending along both the first and the second dielectric layers.

2. The method as claimed in claim 1, wherein each of the first and second microelectronic elements has a thickness of less than about 50 microns between the front face and the rear face.

3. The method as claimed in claim 1, wherein at least one of the microelectronic elements includes flash memory.

4. The method of making a stacked microelectronic unit including the method as claimed in claim 1, further comprising, after step (d), severing the stacked microelectronic assembly between the respective confronting first and confronting second edges of at least some of the respective adjacent ones of the first and second microelectronic elements into a plurality of stacked microelectronic units, each unit including at least one first microelectronic element and at least one second microelectronic element.

5. The method as claimed in claim 1, wherein the at least one opening includes channels extending between the respective confronting first and confronting second edges of at least some of the respective adjacent ones of the first and second microelectronic elements.

6. The method as claimed in claim 1, wherein the openings include a plurality of spaced apart openings aligned with edges of the first and second microelectronic elements and the leads extend within respective individual ones of the spaced apart openings, each lead being conductively connected with a single one of the traces.

7. The method as claimed in claim 1, wherein the opening extends a distance along the respective entire confronting first and entire confronting second edges of at least some of the respective adjacent ones of the first microelectronic elements and the confronting edges of the adjacent ones of the second microelectronic elements.

8. The method as claimed in claim 1, wherein the step of forming leads is performed after the attaching of the plurality of spaced apart second microelectronic elements to the first subassembly.

9. The method as claimed in claim 1, wherein at least one of the plurality of first microelectronic elements and the plurality second microelectronic elements form portions of a reconstituted wafer.