Methods of forming lines of capacitorless one transistor DRAM cells, methods of patterning substrates, and methods of forming two conductive lines

• US 8,551,823 B2
• Filed: 04/29/2009
• Issued: 10/08/2013
• Est. Priority Date: 07/17/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US12/432,497
• Publication Number:
  US 20090239343A1
• Time in Patent Office: 1,623 Days
• Field of Search: 257/213, 257/288, 257/296, 257/347, 257/348, 257/349, 257/350, 257/E21.001, 257/E21.002, 257/E21.04, 257/E21.085, 257/E21.394, 257/E21.4, 257/E21.409, 257/E21.421, 257/E27.001, 257/E27.009, 257/E27.01, 257/E27.07, 257/E27.081, 257/E27.084, 257/E27.085, 438/142, 438/149, 438/151, 438/584, 438/585, 438/595, 438/596
• US Class Current: 438/149
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart from and capacitively coupled to the body region between the source/drain regions. A pair of opposing conductively interconnected second gates are spaced from and received laterally outward of the first gate. The second gates are spaced from and capacitively coupled to the body region laterally outward of the first gate and between the pair of source/drain regions. Methods of forming lines of capacitorless one transistor DRAM cells are disclosed.

Claims

1. A method of forming a series of capacitorless one transistor DRAM cells, comprising:

forming a series of spaced islands of semiconductive material relative to a substrate;

forming a word line which extends over the series of spaced islands, the word line being formed over and capacitively coupled to an electrically floating body region of the respective spaced islands;

forming a pair of conductively interconnected gate lines extend at least partially over the series of spaced islands on opposite sides of the word line and which are electrically isolated from the word line, the pair of gates lines being received over and capacitively coupled to respective floating body regions of the respective spaced islands; and

forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the pair of gate lines.

2. The method of claim 1 wherein the source/drain regions are formed after forming the pair of interconnected gate lines.

3. The method of claim 1 comprising forming a first conductive contact to the word line and a second conductive contact to the pair of gate lines.

4. The method of claim 1 wherein the word line is formed to have an end and forming a respective end of the pair of gate lines that is proximate the word line end, the word line end not being longitudinally co-located with either of said gate line ends.

5. The method of claim 1 comprising:

providing insulative material laterally about and beneath the respective islands and contacting semiconductive material of the respective islands; and

providing conductively doped semiconductive material laterally about and beneath the island outwardly of the insulative material.

6. The method of claim 1 wherein forming the conductively interconnected gate lines comprises:

forming a masking block over a conductive layer and the word line, the masking block having spaced opposing lateral edges;

after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the conductive layer; and

after the heating, etching the conductive layer using the masking block as a mask to form said pair of gate lines.

7. The method of claim 6 wherein the word line is formed to have an end and forming the conductively interconnected gate lines forms a respective end of the pair of gate lines that is proximate the word line end, the word line end not being longitudinally co-located with either of said gate line ends.

8. A method of forming a series of capacitorless one transistor DRAM cells, comprising:

forming a series of spaced islands of semiconductive material relative to a substrate;

forming a word line which extends over the series of spaced islands, the word line being formed over and capacitively coupled to an electrically floating body region of the respective spaced islands and comprising an end;

forming a pair of conductively interconnected gate lines which extend at least partially over the series of spaced islands on opposite sides of the word line and which are electrically isolated from the word line, the pair of gates lines being received over and capacitively coupled to respective floating body regions of the respective spaced islands, respective ends of the pair of gate lines being proximate the word line end, the patterning resulting in the word line extending longitudinally beyond the respective ends of the pair of gate lines; and

forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the pair of gate lines.

9. The method of claim 8 comprising:

providing insulative material laterally about and beneath the respective islands and contacting semiconductive material of the respective islands; and

providing conductively doped semiconductive material laterally about and beneath the island outwardly of the insulative material.

10. The method of claim 8 comprising forming a first conductive contact to the word line and a second conductive contact to the pair of gate lines.

11. The method of claim 10 comprising forming the first conductive contact to some portion of the word line extending longitudinally beyond the respective ends of the pair of gate lines.

12. A method of forming a series of capacitorless one transistor DRAM cells, comprising:

forming a series of spaced islands of silicon-comprising semiconductive material relative to a substrate;

forming a word line which is common to and extends over the line of spaced islands, the word line being formed over an electrically floating body region of the respective spaced islands;

forming a conductive layer over and spaced from the word line;

forming a masking block over the conductive layer and the word line, the masking block having spaced opposing lateral edges;

after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the conductive layer;

after the heating, etching the conductive layer using the masking block as a mask to form a pair of interconnected gate lines which are common to and extend over the series of spaced islands on opposite sides of the word line, the pair of gates lines being received over respective floating body regions of the respective spaced islands; and

forming respective pairs of spaced source/drain regions within the semiconductive material of the respective islands, the pairs of spaced source/drain regions including portions formed laterally outward of the interconnected pair of gate lines.

13. A method of patterning a substrate, comprising:

forming a raised feature relative to a substrate, the raised feature comprising a top and opposing sidewalls;

forming a layer to be patterned over the top and opposing sidewalls of the raised feature;

forming a masking block over the layer, the masking block having spaced opposing lateral edges that are received laterally inward of the opposing sidewalls of the raised feature;

after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the layer and laterally outward beyond the opposing sidewalls of the raised feature; and

after the heating, etching the layer using the masking block as a mask to leave the layer received over the top and opposing sidewalls of the raised feature.

14. The method of claim 13 wherein the masking block is taller than the feature is raised relative to the substrate.

15. The method of claim 13 wherein the opposing lateral edges are each moved laterally outward a distance substantially equal to thickness of the layer.

16. The method of claim 13 wherein the masking block comprises photoresist, and the opposing lateral edges are each moved laterally outward a distance substantially equal to thickness of the layer.

17. The method of claim 13 wherein the masking block comprises photoresist.

18. The method of claim 17 wherein the heating is to about 150°

C.

19. The method of claim 18 wherein the heating is for from about one to about three minutes.

20. A method of forming two conductive lines, comprising:

forming a raised first conductive line over a substrate;

insulating a top and sidewalls of the raised conductive line;

forming conductive material over the insulated top of the raised first conductive line;

forming a masking block over the conductive material, the masking block having spaced opposing lateral edges;

after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the conductive material; and

after the heating, etching the conductive material using the masking block as a mask to form a second conductive line over and electrically isolated from the first conductive line.

21. The method of claim 20 wherein the second conductive line is received laterally over the sidewalls of the first conductive line.

22. The method of claim 20 wherein the masking block comprises photoresist.

23. The method of claim 20 wherein the masking block is taller than the first conductive line is raised relative to the substrate.

24. The method of claim 20 wherein the opposing lateral edges are each moved laterally outward a distance substantially equal to thickness of the conductive material.

25. The method of claim 20 wherein the heating moves the opposing lateral edges of the masking block laterally outward to locations that are laterally outward of first conductive line.

26. A method of patterning a substrate, comprising:

forming a raised feature relative to a substrate;

forming a layer to be patterned over the raised feature, an outer surface of the layer having laterally opposed curved portions where the outer surface curves to extend elevationally inward along opposing sidewalls of the raised feature;

forming a masking block over the layer, the masking block having spaced opposing lateral edges;

after forming the masking block, heating the masking block to move the opposing lateral edges laterally outward further away from one another over the layer, the opposing lateral edges each being moved laterally outward to the laterally opposed curved portions of the outer surface of the layer; and

after the heating, etching the layer using the masking block as a mask to leave the layer received over the raised feature.

27. The method of claim 26 wherein the masking block is taller than the feature is raised relative to the substrate.