Silicon germanium and polysilicon gate structure for strained silicon transistors

• US 8,551,831 B2
• Filed: 09/19/2008
• Issued: 10/08/2013
• Est. Priority Date: 08/10/2007
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Beijing) Corporation (Semiconductor Manufacturing International Corporation), Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: Gao, Da Wei, Zhu, Bei, Wu, Hanming, Chen, John, Bonfanti, Paolo
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): McCall Shepard, Sonya D
• Application Number:
  US12/234,393
• Publication Number:
  US 20090152599A1
• Time in Patent Office: 1,845 Days
• Field of Search: 438/199, 257/288, 257/E21.431, 257/E29.255
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.

Claims

1. A method for forming an integrated circuit semiconductor device comprising:

providing a semiconductor substrate;

forming a dielectric layer overlying the semiconductor substrate;

forming a gate layer overlying the dielectric layer;

patterning the gate layer to form a gate structure including edges;

forming a second dielectric layer overlying the gate structure to protect the gate structure including the edges;

patterning the second dielectric layer to form sidewall spacer structures on the edges of the gate structure;

etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer;

etching a portion of the gate structure to form a recessed region within the sidewall spacer structures;

depositing a silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region and into the recessed region in the gate structure; and

causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region;

wherein etching a source region and a drain region and etching a portion of the gate structure are performed simultaneously,

wherein the silicon germanium material filled in the recessed region forms an integrated gate structure, the integrated gate structure has a lower sheet resistance than a polysilicon layer, and

wherein the gate structure has a remaining thickness of 100 Angstroms and greater after forming the recessed region.

2. The method of claim 1 wherein the second dielectric layer is less than 300 Angstroms.

3. The method of claim 1 wherein the channel region has a length of a width of the gate structure.

4. The method of claim 1 wherein the semiconductor substrate is silicon material.

5. The method of claim 1 wherein the silicon germanium material is single crystalline and the silicon germanium material is simultaneously deposited in the etched source region, etched drain region, and the recessed region.

6. The method of claim 1 wherein the silicon germanium material has a ratio of silicon/germanium of 7/3 to 9/1.

7. The method of claim 1 further comprising forming a silicided metal layer overlying the gate structure.

8. The method of claim 7 wherein the silicided metal layer is a nickel bearing material.

9. The method of claim 1 wherein the depositing is provided using an epitaxial reactor.

10. The method of claim 1 wherein the compressive mode increases a mobility of holes in the channel region.

11. The method of claim 1 wherein the integrated gate structure has a sheet resistivity of 20 ohm/square and less.

12. The method of claim 1 wherein the etching of the gate structure removes a thickness of the gate layer.

13. The method of claim 1 wherein the gate layer has an initial thickness of about 800 Angstroms to 2000 Angstroms.

14. The method of claim 1 wherein the silicon germanium fill material in the gate structure has a boron bearing impurity.

15. The method of claim 1 further comprising forming a nickel germanium silicide overlying the silicon germanium on the gate layer.

16. The method of claim 1 wherein the silicon germanium material is epitaxially deposited using an in-situ doping technique.

17. The method of claim 16 wherein the in-situ doping technique comprises boron having a concentration ranging from about 1×

10¹⁹ to about 1×

10²⁰ atoms/cm³.

18. The method of claim 1 wherein the etched source and drain regions comprise a depth in the range from about 100 Angstroms to about 1000 Angstroms.