Methods of forming CMOS semiconductor devices

• US 8,551,843 B1
• Filed: 05/07/2012
• Issued: 10/08/2013
• Est. Priority Date: 05/07/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cai, Xiuyu, Xie, Ruilong
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): Rundio, Regan J
• Application Number:
  US13/465,486
• Time in Patent Office: 519 Days
• Field of Search: 438/199, 438/294, 438/692, 438/706, 438/717
• US Class Current: 438/294
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.

Claims

1. A method, comprising:

forming first, second and third gate stacks, said first and second gate stacks being positioned above separated active regions in a semiconducting substrate, said third gate stack being an isolation stack positioned above an isolation structure formed in said semiconducting substrate, wherein each of said gate stacks is comprised of at least a layer of gate electrode material, a first layer of hard mask material positioned above said layer of gate electrode material, a second layer of hard mask material positioned above said first layer of hard mask material and a third layer of hard mask material positioned above said second layer of hard mask material, wherein said second layer of hard mask material is comprised of a material that may be selectively etched relative to said first and third layers of hard mask material;

with said first gate stack and said isolation gate stack masked, performing a first etching process on a layer of spacer material to form sidewall spacers positioned proximate said second gate stack;

after forming said sidewall spacers, performing a second etching process to remove said second layer of hard mask material in said second gate stack, thereby exposing said first layer of hard mask material in said second gate stack;

forming an etch stop layer above said first gate stack, said second gate stack and said isolation gate stack;

with said second gate stack and said isolation gate stack masked, performing at least one third etching process on said etch stop layer and on said layer of spacer material to form sidewall spacers positioned proximate said first gate stack, said at least one third etching process exposing said second layer of hard mask material in said first gate stack;

performing a fourth etching process to remove said second layer of hard mask material in said first gate stack, thereby exposing said first layer of hard mask material in said first gate stack;

forming a polish stop layer between said plurality of gate stacks, an upper surface of said polish stop layer being positioned at a level that is above a level of an upper surface of said layer of gate electrode material in each of said gate stacks;

performing at least one fifth etching process on said etch stop layer, said layer of spacer material, and said second layer of hard mask material positioned above or proximate said isolation gate stack, said at least one fifth etching process exposing said first layer of hard mask material in said isolation gate stack; and

performing at least one chemical mechanical polishing process to remove material positioned above said upper surface of said polish stop layer.

2. The method of claim 1, further comprising removing said polish stop layer.

3. The method of claim 1, wherein said polish stop layer is comprised of a flowable oxide material.

4. The method of claim 1, wherein said first gate stack is a gate stack for an NMOS transistor and said second gate stack is a gate stack for a PMOS transistor.

5. The method of claim 1, wherein said first gate stack is a gate stack for a PMOS transistor and said second gate stack is a gate stack for an NMOS transistor.

6. The method of claim 1, wherein said first and third layers of hard mask material are comprised of silicon nitride and said second layer of hard mask material is comprised of a carbon-based material.

7. The method of claim 6, wherein said carbon-based material is one of undoped carbon or a doped carbon.

8. A method, comprising:

forming first, second and third gate stacks, said first and second gate stacks being positioned above separated active regions in a semiconducting substrate, said third gate stack being an isolation stack positioned above an isolation structure formed in said semiconducting substrate, wherein each of said gate stacks is comprised of at least a layer of gate electrode material, a first hard mask layer comprised of silicon nitride positioned above said layer of gate electrode material, a second hard mask layer comprised of a carbon-based material positioned above said first hard mask layer and a third hard mask layer comprised of silicon nitride positioned above said second hard mask layer;

with said first gate stack and said isolation gate stack masked, performing a first etching process on a layer of spacer material to form sidewall spacers positioned proximate said second gate stack;

after forming said sidewall spacers, performing a second etching process to remove said second hard mask layer in said second gate stack, thereby exposing said first hard mask layer in said second gate stack;

forming an etch stop layer above said first gate stack, said second gate stack and said isolation gate stack;

with said second gate stack and said isolation gate stack masked, performing at least one third etching process on said etch stop layer and on said layer of spacer material to form sidewall spacers positioned proximate said first gate stack, said at least one third etching process exposing said second hard mask layer in said first gate stack;

performing a fourth etching process to remove said second hard mask layer in said first gate stack, thereby exposing said first hard mask layer in said first gate stack;

forming a polish stop layer between said plurality of gate stacks, an upper surface of said polish stop layer being positioned at a level that is above a level of an upper surface of said layer of gate electrode material in each of said gate stacks;

performing at least one fifth etching process on said etch stop layer, said layer of spacer material, and said second hard mask layer positioned above or proximate said isolation gate stack, said at least one fifth etching process exposing said first hard mask layer in said isolation gate stack; and

performing at least one chemical mechanical polishing process to remove material positioned above said upper surface of said polish stop layer.

9. The method of claim 8, further comprising removing said polish stop layer.

10. The method of claim 8, wherein said first gate stack is a gate stack for an NMOS transistor and said second gate stack is a gate stack for a PMOS transistor.

11. The method of claim 8, wherein said first gate stack is a gate stack for a PMOS transistor and said second gate stack is a gate stack for an NMOS transistor.

12. The method of claim 8, wherein said carbon-based material is one of undoped carbon or a doped carbon.

13. A method, comprising:

forming an isolation structure in a semiconducting substrate, said isolation structure dividing said substrate into separated active regions;

performing at least one etching process on a stack of materials to define a first gate stack positioned above one of said active regions, a second gate stack positioned above the other of said active regions and an isolation gate stack positioned above said isolation structure, wherein each of said gate stacks is comprised of at least a layer of gate electrode material, a first layer of hard mask material positioned above said layer of gate electrode material, a second layer of hard mask material positioned above said first layer of hard mask material and a third layer of hard mask material positioned above said second layer of hard mask material, wherein said second layer of hard mask material is comprised of a material that may be selectively etched relative to said first and third layers of hard mask material;

forming a layer of spacer material above said first gate stack, said second gate stack and said isolation gate stack;

forming a first masking layer above said isolation gate stack and said first gate stack, said first masking layer exposing said second gate stack for further processing;

with said first masking layer in place, performing a first etching process on said layer of spacer material to form sidewall spacers positioned proximate said second gate stack;

after forming said sidewall spacers, performing a second etching process to remove said second layer of hard mask material in said second gate stack, thereby exposing said first layer of hard mask material in said second gate stack;

removing said first masking layer;

forming an etch stop layer above said first gate stack, said second gate stack and said isolation gate stack;

forming a second masking layer above said isolation gate stack and said second gate stack, said second masking layer exposing said first gate stack for further processing;

with said second masking layer in place, performing at least one third etching process on said etch stop layer and on said layer of spacer material to form sidewall spacers positioned proximate said first gate stack, said at least one third etching process exposing said second layer of hard mask material in said first gate stack;

performing a fourth etching process to remove said second layer of hard mask material in said first gate stack, thereby exposing said first layer of hard mask material in said first gate stack;

after removing said second layer of hard mask material from above said first gate stack, removing said second masking layer;

forming a polish stop layer between said plurality of gate stacks, an upper surface of said polish stop layer being positioned at a level that is above a level of an upper surface of said layer of gate electrode material in each of said gate stacks;

performing at least one fifth etching process on said etch stop layer, said layer of spacer material, and said second layer of hard mask material positioned above or proximate said isolation gate stack, said at least one fifth etching process exposing said first layer of hard mask material in said isolation gate stack; and

performing at least one chemical mechanical polishing process to remove material positioned above said upper surface of said polish stop layer.

14. The method of claim 13, further comprising removing said polish stop layer.

15. The method of claim 13, wherein said polish stop layer is comprised of a flowable oxide material.

16. The method of claim 13, wherein said first gate stack is a gate stack for an NMOS transistor and said second gate stack is a gate stack for a PMOS transistor.

17. The method of claim 13, wherein said first gate stack is a gate stack for a PMOS transistor and said second gate stack is a gate stack for an NMOS transistor.

18. The method of claim 13, wherein said first and third layers of hard mask material are comprised of silicon nitride and said second layer of hard mask material is comprised of a carbon-based material.