×

Methods of forming CMOS semiconductor devices

  • US 8,551,843 B1
  • Filed: 05/07/2012
  • Issued: 10/08/2013
  • Est. Priority Date: 05/07/2012
  • Status: Active Grant
First Claim
Patent Images

1. A method, comprising:

  • forming first, second and third gate stacks, said first and second gate stacks being positioned above separated active regions in a semiconducting substrate, said third gate stack being an isolation stack positioned above an isolation structure formed in said semiconducting substrate, wherein each of said gate stacks is comprised of at least a layer of gate electrode material, a first layer of hard mask material positioned above said layer of gate electrode material, a second layer of hard mask material positioned above said first layer of hard mask material and a third layer of hard mask material positioned above said second layer of hard mask material, wherein said second layer of hard mask material is comprised of a material that may be selectively etched relative to said first and third layers of hard mask material;

    with said first gate stack and said isolation gate stack masked, performing a first etching process on a layer of spacer material to form sidewall spacers positioned proximate said second gate stack;

    after forming said sidewall spacers, performing a second etching process to remove said second layer of hard mask material in said second gate stack, thereby exposing said first layer of hard mask material in said second gate stack;

    forming an etch stop layer above said first gate stack, said second gate stack and said isolation gate stack;

    with said second gate stack and said isolation gate stack masked, performing at least one third etching process on said etch stop layer and on said layer of spacer material to form sidewall spacers positioned proximate said first gate stack, said at least one third etching process exposing said second layer of hard mask material in said first gate stack;

    performing a fourth etching process to remove said second layer of hard mask material in said first gate stack, thereby exposing said first layer of hard mask material in said first gate stack;

    forming a polish stop layer between said plurality of gate stacks, an upper surface of said polish stop layer being positioned at a level that is above a level of an upper surface of said layer of gate electrode material in each of said gate stacks;

    performing at least one fifth etching process on said etch stop layer, said layer of spacer material, and said second layer of hard mask material positioned above or proximate said isolation gate stack, said at least one fifth etching process exposing said first layer of hard mask material in said isolation gate stack; and

    performing at least one chemical mechanical polishing process to remove material positioned above said upper surface of said polish stop layer.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×